Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX D. CIRCUIT LAYOUT CASE STUDIES 269
block mux (int b) (wire s) (wire d0[b], wire d1[b]) ∼ (wire o[b]) {
int j.
for j = 0..b−1 {
(d0[j ], d1[j ]) ; mux lut s ; (o[j ]) at (0, j).
} .
}
block mux ff (wire clk) (int b) (wire s) (wire d0[b], wire d1[b]) ∼ (wire o[b]) {
int j.
for j = 0..b−1 {
(d0[j ], d1[j ]) ; mux lut ff clk s ; (o[j ]) at (0, j).
} .
}
block max2 (int bits) (wire a[bits ], wire b[bits ]) ∼ (wire c[bits ]) {
wire a geq b[bits+1].
int j.
a geq b[0] = true.
for j = 0..bits−1 {
((a[j ], b[j ]) , a geq b[j]) ; comp lut ;a geq b[j+1] at (0, j).
} .
(b, a) ; mux bits (a geq b[bits]) ; c at (1, 0).
}
block min2 (int bits) (wire a[bits ], wire b[bits ]) ∼ (wire c[bits ]) {
wire a geq b[bits+1].
int j.
a geq b[0] = true.
for j = 0..bits−1 {
((a[j ], b[j ]) , a geq b[j]) ; comp lut ;a geq b[j+1] at (0, j).
} .
(a, b) ; mux bits (a geq b[bits]) ; c at (1,0).
}
block eq (int n) (wire a[n], wire b[n]) ∼ (wire c) {
int j.
wire match[n+1].
match[0] = true.
for j = 0..n−1 {
(match[j], a[j ], b[j ]) ; and3 ; (match[j+1]) at (0, j).
} .
c = match[n].
}
/∗∗ Insertion sort ∗/
block insert (int bits) (int n) (‘t a, ‘t b[n]) ∼ (‘t c[n+1]) →
row (n, fork ; [min2 bits, max2 bits]) ; apr n.
block lct cell (int bits) ((wire f, ‘t a), ‘t s) ∼ (wire d, (wire f2,‘t a2)) {
wire a eq s.
a2 = a.
d = f.
(a, s) ; eq bits ; a eq s at (0, height((a eq s, f) ;or2 ; f2)).
(a eq s, f) ; or2 ; f2 at (0, 0).
}