Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Appendix D
Circuit Layout Case Studies
This appendix contains the Quartz descriptions and layout verification proofs for a number of
full hardware designs for the Xilinx Virtex II FPGA architecture. Proof scripts for hardware
primitives have sometimes been omitted, although they have proof scripts and theorems
generated like any other block (though empty structures). Useful layout reasoning is at the
level of half-slices which have size 1 × 1.
D.1 Median Filter
D.1.1 Quartz Description
/∗∗ Median filter in Quartz.
@author Oliver Pell
1−D median filter implemented as a state machine with single serial input.
∗/
directive vhdl ”target:virtex2”.
directive vhdl ”include:ieee header”.
#include ”p prelude.qtz”
/∗ Primitives ∗/
block or2 (wire a, wire b) ∼ (wire c) attributes { height=1. width=1. }{ }
block and2 (wire a, wire b) ∼ (wire c) attributes { height=1. width=1. }{ }
block and3 (wire a, wire b, wire c) ∼ (wire d) attributes { height=1. width=1. }{ }
block fd (wire c) (wire d) ∼ (wire q) attributes { height=1. width=1. }{ }
block inv (wire a) ∼ (wire b) attributes { height=1. width=1. }{ }
block mux lut (wire s) (wire d0, wire d1) ∼ (wire o) attributes { height=1. width=1. }{ }
block mux lut ff (wire clk) (wire s) (wire d0, wire d1) ∼ (wire o) attributes { height=1.
width=1. }{ }
block comp lut ((wire a, wire b), wire s) ∼ (wire o) attributes { height=1. width=1. }{ }
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