Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX C. PLACED COMBINATOR LIBRARIES 262 )" let st1_in = (THE (st1_in::(’t20)vector). EX (st2_in::(’t20)vector) (st1_out::’ t20) (st2_out::’t20). Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) & (if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out) else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & ( struct n R st2_in st2_out)) ) in let st2_in = (THE (st2_in::(’t20)vector). EX (st1_in::(’t20)vector) (st1_out::’ t20) (st2_out::’t20). Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) & (if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out) else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & ( struct n R st2_in st2_out)) ) in let st1_out = (THE (st1_out::’t20). EX (st1_in::(’t20)vector) (st2_in::(’t20) vector) (st2_out::’t20). Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) & (if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out) else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & ( struct n R st2_in st2_out)) ) in let st2_out = (THE (st2_out::’t20). EX (st1_in::(’t20)vector) (st2_in::(’t20) vector) (st1_out::’t20). Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) & (if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out) else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & ( struct n R st2_in st2_out)) ) in max (Width (i ;;; half $ (m div 2) ;;; (st1_in, st2_in))) (if ((Suc n) mod 2) = 0 then max ((width n R st1_in st1_out) + (Width ((st1_out, st2_out) ;;; R ;;; o_)) + (width n R st2_in st2_out)) ((max ((width n R st1_in st1_out) + (Width ((st1_out, st2_out) ;;; R ;;; o_))) (width n R st1_in st1_out))) else max ( width n R st2_in st2_out) ((max (Width ((st1_out, st2_out) ;;; R ;;; o_)) ( width n R st1_in st1_out)))) section {* Validity <strong>of</strong> width and height functions *} theorem height_ge0_int [rule_format]: "!! (n::nat) (R::(((’t20*’t20)=>’t20=>bool,(’ t20*’t20)=>’t20=>int)block)). [| ALL (qs67::(’t20*’t20)) (qs68::’t20). 0 ALL i o_. 0 ’t20=>bool,(’t20 *’t20)=>’t20=>int)block)). [| ALL (qs67::(’t20*’t20)) (qs68::’t20). 0
APPENDIX C. PLACED COMBINATOR LIBRARIES 263 apply (induct_tac n) apply (auto intro: z_aleq_bc half.height_ge0 half.width_ge0 simp add: Let_def max_def half_def) done section {* Additional simplification rules for different representations *} theorem height_ge0: "!! (n::int) (R::(((’t20*’t20)=>’t20=>bool,(’t20*’t20)=>’t20=>int )block)) (i::(’t20)vector) (o_::’t20). [| ALL (qs67::(’t20*’t20)) (qs68::’t20). 0 bool,(’t20*’t20)=>’t20=>int) block)) (i::(’t20)vector) (o_::’t20). [| ALL (qs67::(’t20*’t20)) (qs68::’t20). 0 bool,(’t20*’t20)=>’t20=>int)block)) (i ::(’t20)vector) (o_::’t20). [| if n = 0 then o_ = i else Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) & (if (n mod 2) = 0 then (struct (int2nat (n - 1)) R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (struct (int2nat (n - 1)) R st2_in st2_out) else (struct (int2nat (n - 1)) R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (struct (int2nat (n - 1)) R st2_in st2_out)) ; m = (2 pwr n) ; ALL (qs67::(’t20*’t20)) (qs68::’t20). 0
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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