Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ...
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APPENDIX C. PLACED COMBINATOR LIBRARIES 262<br />
)"<br />
let st1_in = (THE (st1_in::(’t20)vector). EX (st2_in::(’t20)vector) (st1_out::’<br />
t20) (st2_out::’t20).<br />
Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) &<br />
(if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out,<br />
st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out)<br />
else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (<br />
struct n R st2_in st2_out))<br />
) in<br />
let st2_in = (THE (st2_in::(’t20)vector). EX (st1_in::(’t20)vector) (st1_out::’<br />
t20) (st2_out::’t20).<br />
Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) &<br />
(if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out,<br />
st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out)<br />
else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (<br />
struct n R st2_in st2_out))<br />
) in<br />
let st1_out = (THE (st1_out::’t20). EX (st1_in::(’t20)vector) (st2_in::(’t20)<br />
vector) (st2_out::’t20).<br />
Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) &<br />
(if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out,<br />
st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out)<br />
else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (<br />
struct n R st2_in st2_out))<br />
) in<br />
let st2_out = (THE (st2_out::’t20). EX (st1_in::(’t20)vector) (st2_in::(’t20)<br />
vector) (st1_out::’t20).<br />
Def (i ;;; half $ (m div 2) ;;; (st1_in, st2_in)) &<br />
(if ((Suc n) mod 2) = 0 then (struct n R st1_in st1_out) & Def ((st1_out,<br />
st2_out) ;;; R ;;; o_) & (struct n R st2_in st2_out)<br />
else (struct n R st1_in st1_out) & Def ((st1_out, st2_out) ;;; R ;;; o_) & (<br />
struct n R st2_in st2_out))<br />
) in<br />
max (Width (i ;;; half $ (m div 2) ;;; (st1_in, st2_in))) (if ((Suc n) mod 2) = 0<br />
then max ((width n R st1_in st1_out) + (Width ((st1_out, st2_out) ;;; R ;;;<br />
o_)) + (width n R st2_in st2_out)) ((max ((width n R st1_in st1_out) + (Width<br />
((st1_out, st2_out) ;;; R ;;; o_))) (width n R st1_in st1_out))) else max (<br />
width n R st2_in st2_out) ((max (Width ((st1_out, st2_out) ;;; R ;;; o_)) (<br />
width n R st1_in st1_out))))<br />
section {* Validity <strong>of</strong> width and height functions *}<br />
theorem height_ge0_int [rule_format]: "!! (n::nat) (R::(((’t20*’t20)=>’t20=>bool,(’<br />
t20*’t20)=>’t20=>int)block)). [| ALL (qs67::(’t20*’t20)) (qs68::’t20). 0 <br />
ALL i o_. 0 ’t20=>bool,(’t20<br />
*’t20)=>’t20=>int)block)). [| ALL (qs67::(’t20*’t20)) (qs68::’t20). 0
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