Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX C. PLACED COMBINATOR LIBRARIES 260
by auto
end
C.5 H-Tree
block htree (int n, block R (‘a, ‘a) ∼ ‘a) (‘a i [m]) ∼ (‘a o)
{
const m = 2 ∗∗ n.
‘a st1 in[m/2], st2 in[m/2], st1 out, st2 out.
if n == 0 {
o = i[0] .
} else {
i ; half (m/2) ; (st1 in, st2 in)
at (0,0).
if (n mod 2 == 0) {
// Vertical sub−tree arrangement
st1 in ; htree (n−1, R) ; st1 out
at (0,0).
(st1 out, st2 out) ; R ; o
at (0, height(st1 in ; htree (n−1, R) ; st1 out)).
st2 in ; htree (n−1, R) ; st2 out
at (0, height(st1 in;htree (n−1, R);st1 out) + height ((st1 out, st2 out);R;o
)).
} else {
// Horizontal sub−tree arrangement
st1 in ; htree (n−1, R) ; st1 out
at (0,0).
(st1 out, st2 out) ; R ; o
at (width(st1 in ;htree (n−1, R) ; st1 out), 0).
st2 in ; htree (n−1, R) ; st2 out
at (width(st1 in;htree (n−1, R);st1 out) + width ((st1 out, st2 out);R;o), 0)
.
} .
} .
}
theory htree = half:
section {* Function definitions *}
consts
struct:: "nat=>(((’t20*’t20)=>’t20=>bool,(’t20*’t20)=>’t20=>int)block)=>(’t20)
vector=>’t20=>bool"
height:: "nat=>(((’t20*’t20)=>’t20=>bool,(’t20*’t20)=>’t20=>int)block)=>(’t20)
vector=>’t20=>int"
width:: "nat=>(((’t20*’t20)=>’t20=>bool,(’t20*’t20)=>’t20=>int)block)=>(’t20)
vector=>’t20=>int"
htree:: "((int*(((’t20*’t20)=>’t20=>bool,(’t20*’t20)=>’t20=>int)block))=>(’t20)
vector=>’t20=>bool, (int*(((’t20*’t20)=>’t20=>bool,(’t20*’t20)=>’t20=>int)
block))=>(’t20)vector=>’t20=>int)block"
defs
htree_def: "htree == (| Def = % (n, R) i o_. struct (int2nat n) R i o_, Height =
% (n, R) i o_. height (int2nat n) R i o_, Width = % (n, R) i o_. width (
int2nat n) R i o_|)"