Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX C. PLACED COMBINATOR LIBRARIES 237
apply (simp (no_asm_simp) del: height_def width_def add: Let_def max_def converse_def
pi2_def irdlelem_def,
(rule height_ge0_int, (simp+)?)?)
done
theorem width_ge0: "!! (R::((int=>(’t36*’t28)=>’t36=>bool,int=>(’t36*’t28)=>’t36=>int
)block)) (n::int) (l::’t36) (t::’t28) (b::’t28) (r::’t36). [| ALL (qs643::int) (
qs644::(’t36*’t28)) (qs645::’t36). 0
0 (’t36*’t28)=>’t36=>bool,int=>(’t36*’t28)=>’t36=>int)block)) (n
::int) (l::’t36) (t::’t28) (b::’t28) (r::’t36). [| Def ((l, t) ;;; R $ n ;;
converse $ (pi2) ;;; (b, r)) ; ALL (qs643::int) (qs644::(’t36*’t28)) (qs645::’
t36). 0 ’t298=>int)
block))=>(’t298*(’t257)vector)=>’t298=>bool"
height:: "(int*((int=>(’t298*’t257)=>’t298=>bool,int=>(’t298*’t257)=>’t298=>int)
block))=>(’t298*(’t257)vector)=>’t298=>int"
width:: "(int*((int=>(’t298*’t257)=>’t298=>bool,int=>(’t298*’t257)=>’t298=>int)
block))=>(’t298*(’t257)vector)=>’t298=>int"
irdl:: "((int*((int=>(’t298*’t257)=>’t298=>bool,int=>(’t298*’t257)=>’t298=>int)
block))=>(’t298*(’t257)vector)=>’t298=>bool, (int*((int=>(’t298*’t257)=>’t298
=>bool,int=>(’t298*’t257)=>’t298=>int)block))=>(’t298*(’t257)vector)=>’t298=>
int)block"
defs
struct_def: "struct == % (n, R) (l, t) r. Def ((l, t) ;;; irow $ (n, irdlelem $ (
R)) ;; pi2 ;;; r)"
height_def: "height == % (n, R) (l, t) r. Height ((l, t) ;;; irow $ (n, irdlelem
$ (R)) ;; pi2 ;;; r)"
width_def: "width == % (n, R) (l, t) r. Width ((l, t) ;;; irow $ (n, irdlelem $ (
R)) ;; pi2 ;;; r)"