Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX C. PLACED COMBINATOR LIBRARIES 230 theorem height_ge0: "!! (n::int) (R::((int=>’t18=>’t18=>bool,int=>’t18=>’t18=>int) block)) (d::’t18) (r::’t18). [| ALL (qs23::int) (qs24::’t18) (qs25::’t18). 0 bool,int=>’t18=>’t18=>int) block)) (d::’t18) (r::’t18). [| ALL (qs23::int) (qs24::’t18) (qs25::’t18). 0 bool,int=>’t18=>’t18=>int)block)) (d::’ t18) (r::’t18). [| if n = 0 then d = r else Def (d ;;; ichain $ (n - 1, R) ;; R $ n ;;; r) ; ALL (qs23::int) (qs24::’t18) (qs25::’t18). 0
APPENDIX C. PLACED COMBINATOR LIBRARIES 231 section {* Function definitions *} consts struct:: "nat=>((int=>’t106=>’t106=>bool,int=>’t106=>’t106=>int)block)=>(’t106) vector=>(’t106)vector=>bool" height:: "nat=>((int=>’t106=>’t106=>bool,int=>’t106=>’t106=>int)block)=>(’t106) vector=>(’t106)vector=>int" width:: "nat=>((int=>’t106=>’t106=>bool,int=>’t106=>’t106=>int)block)=>(’t106) vector=>(’t106)vector=>int" imap:: "((int*((int=>’t106=>’t106=>bool,int=>’t106=>’t106=>int)block))=>(’t106) vector=>(’t106)vector=>bool, (int*((int=>’t106=>’t106=>bool,int=>’t106=>’t106 =>int)block))=>(’t106)vector=>(’t106)vector=>int)block" defs imap_def: "imap == (| Def = % (n, R) d r. struct (int2nat n) R d r, Height = % (n , R) d r. height (int2nat n) R d r, Width = % (n, R) d r. width (int2nat n) R d r |)" primrec "struct 0 R d r = (d = r)" "struct (Suc n) R d r = ( struct n R (d) (r) & Def (d ;;; R $ (int (Suc n)) ;;; r) )" (* Parallel composition laid out vertically, heights add *) primrec "height 0 R d r = 0" "height (Suc n) R d r = ( Height (d ;;; R $ (int (Suc n)) ;;; r) + height n R (d) (r) )" primrec "width 0 R d r = 0" "width (Suc n) R d r = ( max (Width (d ;;; R $ (int (Suc n)) ;;; r)) (width n R (d) (r)) )" section {* Validity <strong>of</strong> width and height functions *} theorem height_ge0_int [rule_format]: "!! (n::nat) (R::((int=>’t31=>’t31=>bool,int=>’ t31=>’t31=>int)block)). [| n >= 0 ; ALL (qs148::int) (qs149::’t31) (qs150::’t31) . 0 ’t31=>bool,int=>’ t31=>’t31=>int)block)). [| n >= 0 ; ALL (qs148::int) (qs149::’t31) (qs150::’t31)
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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Page 191 and 192: BIBLIOGRAPHY 181 [60] L. C. Paulson
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