Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX C. PLACED COMBINATOR LIBRARIES 227
C.1.10 loop
/∗∗ Loop. Ruby x (loop R) y. R for some s. ∗/
block loop (block R (‘a, ˆd1 ‘b) ∼ (ˆd1∗ ‘b, ‘c)) (‘a i) ∼ (‘c o)
attributes {
height = height((i, s) ; R ; (s, o)).
width = width((i, s) ;R ; (s, o)).
layout−proved.
} {
‘b s.
(i, s) ; R ; (s, o) at (0,0).
}
theory loop = QuartzLayout:
section {* Function definitions *}
consts
struct:: "(((’t632*’t633)=>(’t633*’t634)=>bool,(’t632*’t633)=>(’t633*’t634)=>int)
block)=>’t632=>’t634=>bool"
height:: "(((’t632*’t633)=>(’t633*’t634)=>bool,(’t632*’t633)=>(’t633*’t634)=>int)
block)=>’t632=>’t634=>int"
width:: "(((’t632*’t633)=>(’t633*’t634)=>bool,(’t632*’t633)=>(’t633*’t634)=>int)
block)=>’t632=>’t634=>int"
loop:: "((((’t632*’t633)=>(’t633*’t634)=>bool,(’t632*’t633)=>(’t633*’t634)=>int)
block)=>’t632=>’t634=>bool, (((’t632*’t633)=>(’t633*’t634)=>bool,(’t632*’t633
)=>(’t633*’t634)=>int)block)=>’t632=>’t634=>int)block"
defs
struct_def: "struct == % R i o_. EX (s::’t633). Def ((i, s) ;;; R ;;; (s, o_))"
height_def: "height == % R i o_. let s = (THE (s::’t633). Def ((i, s) ;;; R ;;; (
s, o_))) in Height ((i, s) ;;; R ;;; (s, o_))"
width_def: "width == % R i o_. let s = (THE (s::’t633). Def ((i, s) ;;; R ;;; (s,
o_))) in Width ((i, s) ;;; R ;;; (s, o_))"
loop_def: "loop == (| Def = struct, Height = height, Width = width |)"
declare width_def [simp]
declare height_def [simp]
declare struct_def [simp]
section {* Validity of width and height functions *}
theorem height_ge0_int: "!! (R::(((’t632*’t633)=>(’t633*’t634)=>bool,(’t632*’t633)
=>(’t633*’t634)=>int)block)) (i::’t632) (o_::’t634). [| ALL (qs722::(’t632*’t633
)) (qs723::(’t633*’t634)). 0
0 (’t633*’t634)=>bool,(’t632*’t633)=>(’
t633*’t634)=>int)block)) (i::’t632) (o_::’t634). [| ALL (qs722::(’t632*’t633)) (
qs723::(’t633*’t634)). 0
0