Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX C. PLACED COMBINATOR LIBRARIES 222 theorem "!! (R::(((’t486*’t487)=>(’t488*’t489)=>bool,(’t486*’t487)=>(’t488*’t489)=> int)block)) (S::(((’t489*’t491)=>(’t492*’t493)=>bool,(’t489*’t491)=>(’t492*’t493 )=>int)block)) (a::’t486) (b::’t487) (c::’t491) (d::’t488) (e::’t492) (f::’t493) . [| Def ((a, b) ;;; R ;;; (d, is)) ; Def ((is, c) ;;; S ;;; (e, f)) ; ALL ( qs704::(’t486*’t487)) (qs705::(’t488*’t489)). 0
APPENDIX C. PLACED COMBINATOR LIBRARIES 223 struct:: "(int*(((’t520*’t506)=>(’t507*’t520)=>bool,(’t520*’t506)=>(’t507*’t520) =>int)block))=>(’t520*(’t506)vector)=>((’t507)vector*’t520)=>bool" height:: "(int*(((’t520*’t506)=>(’t507*’t520)=>bool,(’t520*’t506)=>(’t507*’t520) =>int)block))=>(’t520*(’t506)vector)=>((’t507)vector*’t520)=>int" width:: "(int*(((’t520*’t506)=>(’t507*’t520)=>bool,(’t520*’t506)=>(’t507*’t520)=> int)block))=>(’t520*(’t506)vector)=>((’t507)vector*’t520)=>int" row:: "((int*(((’t520*’t506)=>(’t507*’t520)=>bool,(’t520*’t506)=>(’t507*’t520)=> int)block))=>(’t520*(’t506)vector)=>((’t507)vector*’t520)=>bool, (int*(((’ t520*’t506)=>(’t507*’t520)=>bool,(’t520*’t506)=>(’t507*’t520)=>int)block)) =>(’t520*(’t506)vector)=>((’t507)vector*’t520)=>int)block" defs struct_def: "struct == % (n, R) (l, t) (b, r). EX (is::(’t520)vector). (is = l ) & (ALL (i::int). ((0 bool,(’t520 *’t506)=>(’t507*’t520)=>int)block)) (l::’t520) (t::(’t506)vector) (b::(’t507) vector) (r::’t520). [| ALL (qs708::(’t520*’t506)) (qs709::(’t507*’t520)). 0 0 (’t507*’t520)=>bool,(’t520*’ t506)=>(’t507*’t520)=>int)block)) (l::’t520) (t::(’t506)vector) (b::(’t507) vector) (r::’t520). [| ALL (qs708::(’t520*’t506)) (qs709::(’t507*’t520)). 0 0 (’t507*’t520)=>bool,(’t520*’ t506)=>(’t507*’t520)=>int)block)) (l::’t520) (t::(’t506)vector) (b::(’t507) vector) (r::’t520). [| ALL (qs708::(’t520*’t506)) (qs709::(’t507*’t520)). 0 0
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Page 185 and 186: Bibliography [1] A. Aggoun and N. B
Page 187 and 188: BIBLIOGRAPHY 177 [19] H. Gelernter.
Page 189 and 190: BIBLIOGRAPHY 179 [41] Y. Li and M.
Page 191 and 192: BIBLIOGRAPHY 181 [60] L. C. Paulson
Page 193 and 194: BIBLIOGRAPHY 183 [83] J. Voeten. On
Page 195 and 196: APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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