Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...

24.04.2013 Views

APPENDIX C. PLACED COMBINATOR LIBRARIES 218 section {* Validity of width and height functions *} theorem height_ge0_int: "!! (n::int) (R::((’t415=>’t415=>bool,’t415=>’t415=>int)block )) (i::(’t415)vector) (o_::(’t415)vector). [| ALL (qs694::’t415) (qs695::’t415). 0 0 ’t415=>bool,’t415=>’t415=>int)block) ) (i::(’t415)vector) (o_::(’t415)vector). [| ALL (qs694::’t415) (qs695::’t415). 0 0 ’t415=>bool,’t415=>’t415=>int)block)) ( i::(’t415)vector) (o_::(’t415)vector). [| ALL (qs694::’t415) (qs695::’t415). 0 0 ’t415=>bool,’t415=>’t415=>int)block)) (i ::(’t415)vector) (o_::(’t415)vector). [| ALL (qs694::’t415) (qs695::’t415). 0 0 ’t415=>bool,’t415=>’t415=>int)block)) (i::(’t415) vector) (o_::(’t415)vector). [| n >= 0 ; o_ = i ; if n > 1 then ALL (j:: int). ((1

APPENDIX C. PLACED COMBINATOR LIBRARIES 219 section {* Intersection theorems *} theorem "!! (n::int) (R::((’t415=>’t415=>bool,’t415=>’t415=>int)block)) (i::(’t415) vector) (o_::(’t415)vector). [| n >= 0 ; o_ = i ; if n > 1 then ALL (j:: int). ((1

APPENDIX C. PLACED COMBINATOR LIBRARIES 219<br />

section {* Intersection theorems *}<br />

theorem "!! (n::int) (R::((’t415=>’t415=>bool,’t415=>’t415=>int)block)) (i::(’t415)<br />

vector) (o_::(’t415)vector). [| n >= 0 ; o_ = i ; if n > 1 then ALL (j::<br />

int). ((1

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