Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
CHAPTER 2. BACKGROUND AND RELATED WORK 10 combinators. Lava provides a more sophisticated layout system designed specifically to target Xilinx FPGAs with combinators to place components beside each other, below each other or at the same location. Circuit layouts derived from Ruby relational descriptions can not be invalid, since only beside or below placement is allowed. The Lava system is more powerful and, because it allows components to be placed on top of each other (desirable in order to instantiate the different hardware primitives within a single slice) can generate invalid layouts. 2.1.3 FPGA Architectures The three main companies producing FPGAs commercially are Altera, Actel and Xilinx. Most FPGAs are based on static RAM although Actel produces FPGAs based on antifuses [23]. An antifuse is an electrically programmable two-terminal device which changes from high to low resistance when a programming voltage is applied to it. Actel FPGAs are mainly used in military applications. Altera FPGA architectures are based around simple logic elements which contain a look-up table, flip-flop and some additional circuitry to implement fast-carry chains. Xilinx architec- tures are based around more complex Configurable Logic Blocks, each of which contains four “slices”. Xilinx Virtex-II [86] is a typical family of FPGAs with 11 members, ranging from 40,000 to 8M system gates. The slices within each CLB are arranged in two columns with fast connections between the slices in each column for propagating carry signals. Each slice contains two 4-input function generators, carry logic, logic gates, multiplexers and storage elements. Figure 2.2 shows the circuit diagram of the top half of a slice in the Virtex-II architecture. The 4-input LUTs in each slice are capable of implementing any boolean function of up to four inputs and the propagation delay of the component is independent of the function being implemented. In addition to the basic LUT a component that is particularly worthy of note is the MUXCY multiplexer which permits the implementation of fast carry signals between the slices arranged vertically in a column. The ORCY component and dedicated Sum of
CHAPTER 2. BACKGROUND AND RELATED WORK 11 SOPIN Dual-Port Shift-Reg G4 G3 G2 G1 WG4 WG3 A4 A3 A2 A1 WG4 WG3 LUT RAM ROM G D WG2 WG1 WG2 WG1 MC15 WS DI ALTDIG BY SLICEWE[2:0] CE CLK SR SHIFTIN COUT 0 MULTAND WSG WE[2:0] WE CLK WSF 1 1 0 SHIFTOUT MUXCY 0 1 G2 PROD G1 BY CYOG MUXCY 0 1 Shared between x & y Registers XORG ORCY DYMUX YBMUX CE CLK GYMUX FF LATCH D Q CE CK Y SR REV Figure 2.2: Top half of a Virtex-II slice (Copyright 2000-2005 Xilinx, Inc) SR SOPOUT Products (SOP) chain are designed to support the implementation of large SOP expressions. Some FPGAs include full instruction processors on-chip, in order to provide some additional general purpose computing capability. General purpose processors which incorporate some reconfigurable logic are also under development [4]. These software-configurable processors are designed to combine the benefits of FPGA parallelism with fast general purpose compu- tation to offer significant performance gains. 2.2 Describing Hardware With the increasing complexity of electronic systems computer aided design (CAD) tools have become increasingly important. For decades, hardware was primarily designed using CIN YB Y DY Q DIG
- Page 1 and 2: Imperial College of Science, Techno
- Page 3 and 4: Acknowledgements Firstly, I’d lik
- Page 5 and 6: TABLE OF CONTENTS iv 2.5 Isabelle:
- Page 7 and 8: TABLE OF CONTENTS vi 5.3.1 Speciali
- Page 9 and 10: TABLE OF CONTENTS viii C.1.1 fst .
- Page 11 and 12: Chapter 1 Introduction This thesis
- Page 13 and 14: CHAPTER 1. INTRODUCTION 3 B A C Fig
- Page 15 and 16: CHAPTER 1. INTRODUCTION 5 pler, all
- Page 17 and 18: CHAPTER 2. BACKGROUND AND RELATED W
- Page 19: CHAPTER 2. BACKGROUND AND RELATED W
- Page 23 and 24: CHAPTER 2. BACKGROUND AND RELATED W
- Page 25 and 26: CHAPTER 2. BACKGROUND AND RELATED W
- Page 27 and 28: CHAPTER 2. BACKGROUND AND RELATED W
- Page 29 and 30: CHAPTER 2. BACKGROUND AND RELATED W
- Page 31 and 32: CHAPTER 2. BACKGROUND AND RELATED W
- Page 33 and 34: CHAPTER 2. BACKGROUND AND RELATED W
- Page 35 and 36: CHAPTER 2. BACKGROUND AND RELATED W
- Page 37 and 38: CHAPTER 2. BACKGROUND AND RELATED W
- Page 39 and 40: CHAPTER 2. BACKGROUND AND RELATED W
- Page 41 and 42: CHAPTER 2. BACKGROUND AND RELATED W
- Page 43 and 44: CHAPTER 2. BACKGROUND AND RELATED W
- Page 45 and 46: CHAPTER 3. GENERATING PARAMETERISED
- Page 47 and 48: CHAPTER 3. GENERATING PARAMETERISED
- Page 49 and 50: CHAPTER 3. GENERATING PARAMETERISED
- Page 51 and 52: CHAPTER 3. GENERATING PARAMETERISED
- Page 53 and 54: CHAPTER 3. GENERATING PARAMETERISED
- Page 55 and 56: CHAPTER 3. GENERATING PARAMETERISED
- Page 57 and 58: CHAPTER 3. GENERATING PARAMETERISED
- Page 59 and 60: CHAPTER 3. GENERATING PARAMETERISED
- Page 61 and 62: CHAPTER 3. GENERATING PARAMETERISED
- Page 63 and 64: CHAPTER 3. GENERATING PARAMETERISED
- Page 65 and 66: CHAPTER 3. GENERATING PARAMETERISED
- Page 67 and 68: CHAPTER 3. GENERATING PARAMETERISED
- Page 69 and 70: CHAPTER 3. GENERATING PARAMETERISED
CHAPTER 2. BACKGROUND AND RELATED WORK 11<br />
SOPIN<br />
Dual-Port<br />
Shift-Reg<br />
G4<br />
G3<br />
G2<br />
G1<br />
WG4<br />
WG3<br />
A4<br />
A3<br />
A2<br />
A1<br />
WG4<br />
WG3<br />
LUT<br />
RAM<br />
ROM<br />
G<br />
D<br />
WG2<br />
WG1<br />
WG2<br />
WG1<br />
MC15<br />
WS DI<br />
ALTDIG<br />
BY<br />
SLICEWE[2:0]<br />
CE<br />
CLK<br />
SR<br />
SHIFTIN COUT<br />
0<br />
MULTAND<br />
WSG<br />
WE[2:0]<br />
WE<br />
CLK<br />
WSF<br />
1<br />
1<br />
0<br />
SHIFTOUT<br />
MUXCY<br />
0 1<br />
G2<br />
PROD<br />
G1<br />
BY<br />
CYOG<br />
MUXCY<br />
0 1<br />
Shared between<br />
x & y Registers<br />
XORG<br />
ORCY<br />
DYMUX<br />
YBMUX<br />
CE<br />
CLK<br />
GYMUX<br />
FF<br />
LATCH<br />
D Q<br />
CE<br />
CK<br />
Y<br />
SR REV<br />
Figure 2.2: Top half <strong>of</strong> a Virtex-II slice (Copyright 2000-2005 Xilinx, Inc)<br />
SR<br />
SOPOUT<br />
Products (SOP) chain are designed to support the implementation <strong>of</strong> large SOP expressions.<br />
Some <strong>FPGA</strong>s include full instruction processors on-chip, in order to provide some additional<br />
general purpose computing capability. General purpose processors which incorporate some<br />
reconfigurable logic are also under development [4]. These s<strong>of</strong>tware-configurable processors<br />
are designed to combine the benefits <strong>of</strong> <strong>FPGA</strong> parallelism <strong>with</strong> fast general purpose compu-<br />
tation to <strong>of</strong>fer significant performance gains.<br />
2.2 Describing Hardware<br />
With the increasing complexity <strong>of</strong> electronic systems computer aided design (CAD) tools<br />
have become increasingly important. For decades, hardware was primarily designed using<br />
CIN<br />
YB<br />
Y<br />
DY<br />
Q<br />
DIG
Change language