Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX B. THEORETICAL BASIS FOR LAYOUT REASONING 196 apply (rule conjI) apply (simp) apply (rule impI) apply (simp (no_asm_simp) add: Let_def del: maxf.simps) apply (simp only: z_leqplusone) apply (simp only: logic_rearr) apply (rule allI) apply (rule logic_rearr2) apply (simp only: le_max_iff_disj) apply (simp) apply (simp only: le_max_iff_disj) apply (simp) done theorem maxf_fmax: "!! b t f x. [| b b
APPENDIX B. THEORETICAL BASIS FOR LAYOUT REASONING 197 apply (simp del: maxf.simps) apply (rule conjI) apply (rule impI) defer apply (rule impI) apply (rule exI) apply (rule conjI) defer apply (rule conjI) defer apply (simp) defer by (simp, simp, auto) theorem maxf_is_maxf: "!! b t f. [| b
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 109 opera
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 115 const
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CHAPTER 5. SPECIALISATION 117 block
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 121 Buffe
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CHAPTER 5. SPECIALISATION 123 a fas
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CHAPTER 5. SPECIALISATION 125 block
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CHAPTER 5. SPECIALISATION 127 y y y
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CHAPTER 5. SPECIALISATION 129 with
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CHAPTER 6. LAYOUT CASE STUDIES 131
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Page 185 and 186: Bibliography [1] A. Aggoun and N. B
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Page 191 and 192: BIBLIOGRAPHY 181 [60] L. C. Paulson
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Page 195 and 196: APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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APPENDIX C. PLACED COMBINATOR LIBRA
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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