Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX B. THEORETICAL BASIS FOR LAYOUT REASONING 194
header {* Definition of Quartz parallel composition *}
theory ParallelComposition = Block + IntAlgebra:
consts
Par :: "(’a=>’b=>bool, ’a=>’b=>int)block=>(’c=>’d=>bool,’c=>’d=>int)block=>((’a*’c
)=>(’b*’d)=>bool, (’a*’c)=>(’b*’d)=>int)block"
EmptyPar :: "unit=>unit" ("[[ ]]")
section {* Syntax definitions *}
nonterminals
par_args parpatterns
syntax
"_par" :: "(’a=>’b=>bool,’a=>’b=>int)block => par_args => ((’a*’c)=>(’b*’d)=>
bool,(’a*’c)=>(’b*’d)=>int)block"
("[[ _ , _ ]]")
"_par_arg" :: "(’a=>’b=>bool,’a=>’b=>int)block => par_args" ("_")
"_par_args" :: "(’c=>’d=>bool,’c=>’d=>int)block => par_args => par_args" ("_,/ _
")
"_parpattern" :: "[pttrn, parpatterns] => pttrn" ("’[[_,/ _’]]")
"" :: "pttrn => parpatterns" ("_")
"_parpatterns" :: "[pttrn, parpatterns] => parpatterns" ("_,/ _")
translations
"[[ x, y ]]" == "Par x y"
"_par x (_par_args y z)" == "_par x (_par_arg (_par y z))"
defs
par_def: "Par A B == (| Def = % (d1, d2) (r1, r2). (Def A) d1 r1 & (Def B) d2 r2,
Height = % (d1,d2) (r1, r2). (Height A) d1 r1 + (Height B) d2
r2,
Width = % (d1, d2) (r1, r2). max ((Width A) d1 r1) ((Width B)
d2 r2) |)"
section {* Expansion theorems *}
theorem par2height: "Height (((a,b) ;;; [[ F, G ]] ;;; (c, d))) = (Height F) a c + (
Height G) b d"
by (simp add: par_def)
theorem par2width: "Width ((a,b) ;;; [[ F , G ]] ;;; (c, d)) = max ((Width F) a c) ((
Width G) b d)"
by (simp add: par_def)
section {* Properties of parallel composition *}
theorem width_par_ge0: "!! P Q x y. [| !! x y. 0