Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX B. THEORETICAL BASIS FOR LAYOUT REASONING 193
declare zip_height_def [simp]
declare zip_width_def [simp]
declare zip_def [simp]
section {* Unzip block *}
consts
defs
unzip_struct:: "int=>(’a)vector=>’b=>bool"
unzip_height:: "int=>(’a)vector=>’b=>int"
unzip_width:: "int=>(’a)vector=>’b=>int"
unzip:: "(int=>(’a)vector=>’b=>bool, int=>(’a)vector=>’b=>int)block"
unzip_height_def: "unzip_height == % n x y. 0"
unzip_width_def: "unzip_width == % n x y. 0"
unzip_def: "unzip == (| Def = unzip_struct, Height = unzip_height, Width =
unzip_width|)"
declare unzip_height_def [simp]
declare unzip_width_def [simp]
declare unzip_def [simp]
end
B.5 SeriesComposition
header {* Definition of Quartz series composition *}
theory SeriesComposition = Block + IntAlgebra:
constdefs
ser:: "[(’a=>’b=>bool,’a=>’b=>int)block,(’b=>’c=>bool,’b=>’c=>int)block]=>(’a=>’c
=>bool, ’a=>’c=>int)block" (infixl ";;" 48)
"ser == (% B1 B2. (| Def = % x y. EX s. (Def B1) x s & (Def B2) s y,
Height = % x y. let s = (THE s. (Def B1) x s & (Def B2) s y) in
max (Height B1 x s) (Height B2 s y),
Width = % x y. let s = (THE s. (Def B1) x s & (Def B2) s y) in
(Width B1 x s) + (Width B2 s y)|))"
section {* Properties of series composition *}
theorem width_ser_ge0: "!! P Q x y. [| !! x y. 0