Verification of Parameterised FPGA Circuit Descriptions with Layout ...

APPENDIX B. THEORETICAL BASIS FOR LAYOUT REASONING 192
inst :: "[’a, (’a=>’b=>bool,’a=>’b=>int)block,’b]=>(bool, int)block" ("_ ;;; _ ;;;
_" [45, 46, 47] 45)
"inst == (% x B y. (| Def = Def B x y, Height = Height B x y, Width = Width B x y
|))"
section {* Simplification theorems *}
theorem height_extract [simp]: "Height (x ;;; A ;;; y) = ((Height A) x y)"
by (simp add:inst_def)
theorem width_extract [simp]: "Width (x ;;; A ;;; y) = ((Width A) x y)"
by (simp add:inst_def)
theorem def_extract: "Def (x ;;; A ;;; y) = (Def A) x y"
by (simp add: inst_def)
theorem height_ap [simp]: "Height (A $ x) = (Height A) x"
by (simp add: ap_def)
theorem width_ap [simp]: "Width (A $ x) = (Width A) x"
by (simp add: ap_def)
theorem def_ap [simp]: "Def (A $ x) = (Def A) x"
by (simp add: ap_def)
section {* Congruence, for recdef proofs *}
theorem ap_cong: "((| Def = s, Height = h, Width = w|) $ l) = (| Def = s l, Height =
h l, Width = w l|)"
by (simp)
declare ap_cong [recdef_cong]
end
B.4 Inbuilt
header {* In-built language blocks: zip and unzip *}
theory Inbuilt = Types + Block:
(* Don’t define structure / function - unnecessary for reasoning about size *)
section {* Zip block *}
consts
defs
zip_struct:: "int=>’a=>(’b)vector=>bool"
zip_height:: "int=>’a=>(’b)vector=>int"
zip_width:: "int=>’a=>(’b)vector=>int"
zip:: "(int=>’a=>(’b)vector=>bool, int=>’a=>(’b)vector=>int)block"
zip_height_def: "zip_height == % n x y. 0"
zip_width_def: "zip_width == % n x y. 0"
zip_def: "zip == (| Def = zip_struct, Height = zip_height, Width = zip_width
|)"