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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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APPENDIX B. THEORETICAL BASIS FOR LAYOUT REASONING 191<br />

(* A less permissive version <strong>of</strong> the ’nat(n)’ function. ’nat(n)’ is a total function<br />

*)<br />

(* but we want a partial function defined only for n >= 0 *)<br />

constdefs<br />

int2nat :: "int => nat"<br />

"int2nat == (% x. if 0 int2nat x = arbitrary"<br />

by (simp add: int2nat_def)<br />

theorem int2nat_defined [simp]: "!! (x::int). 0 int2nat x = nat x"<br />

by (simp add: int2nat_def)<br />

end<br />

B.2 Types<br />

header {* Definition <strong>of</strong> Quartz types *}<br />

theory Types = Main:<br />

typedecl wire<br />

types ’a vector = "int => ’a"<br />

constdefs<br />

vecelem :: "’a vector => int => ’a" ("_" [51, 52] 51)<br />

"vecelem == % v i. (v i)"<br />

vecrange:: "’a vector => int => int => ’a vector" ("_" [55,56,57] 55)<br />

"vecrange == % v ub lb. (%x. if (x + lb) wire"<br />

bool2wire :: "bool => wire"<br />

end<br />

B.3 Block<br />

header {* Definition <strong>of</strong> Quartz blocks as records <strong>of</strong> functional definition and size<br />

functions *}<br />

theory Block = Types:<br />

record (’a,’b)block =<br />

Def :: "’a"<br />

Height :: "’b"<br />

Width :: "’b"<br />

section {* Currying <strong>of</strong> blocks and block instantiation *}<br />

constdefs<br />

ap :: "[(’a=>’b,’a=>’c)block,’a]=>(’b,’c)block" (infixl "$" 49)<br />

"ap == % B x. (| Def = Def B x, Height = Height B x, Width = Width B x |)"<br />

constdefs

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