Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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BIBLIOGRAPHY 182 [72] H. Schmit. Extra-dimensional island-style FPGAs. In Proc. FPL 2003: Field Program- mable Logic and Applications, pages 406–415, 2003. [73] C.-J. H. Seger and R. E. Bryant. Formal verification by symbolic evaluation of partially- ordered trajectories. Formal Methods in Systems Design, 6:147–189, 1994. [74] R. Sharp and O. Rasmussen. The T-Ruby design system. Formal Methods in System Design, 11(3):239–264, 1997. [75] M. Sheeran. Finding regularity: Describing and analysing circuits that are not quite regular. In Proc. CHARME’03: Correct Hardware Design and Verification Methods, volume 2860 of LNCS, pages 4–18. Springer-Verlag, 2003. [76] M. Sheeran. Generating fast multipliers using clever circuits. In A. J. Hu and A. K. Martin, editors, Proc. FMCAD 2004: 5th Intl. Conf. Formal Methods in Computer- Aided Design, volume 3312 of LNCS, pages 6–20. Springer-Verlag, 2004. [77] S. Singh. Death of the RLOC? In FCCM’00: Proc. 8th IEEE Symp. on Field- Programmable Custom Computing Machines, page 145, Washington, DC, USA, 2000. IEEE Computer Society. [78] S. Singh and P. James-Roxby. Lava and JBits: From HDL to bitstream in seconds. In Proc. FCCM’01: 9th IEEE Symp. Field-Programmable Custom Computing Machines, 2001. [79] M. K. Srivas and S. P. Miller. Applying formal verification to the AAMP5 microproces- sor: A case study in the industrial use of formal methods. Formal Methods in System Design, 8(2):153–188, 1996. [80] K. W. Susanto and T. Melham. Formally analyzed dynamic synthesis of hardware. J. Supercomputing, 19(1):7–22, 2001. [81] D. E. Thomes and P. Moorby. The Verilog Hardware Description Language. Kluwer Academic, 3rd edition edition, 1996. [82] T. Todman and W. Luk. Combining imperative and declarative hardware descriptions. In Proc. HICSS ’03: 36th Hawaii Intl. Conf. on System Sciences, pages 280–289. IEEE Computer Society, 2003.
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 113 circu
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CHAPTER 5. SPECIALISATION 119 Modif
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CHAPTER 5. SPECIALISATION 129 with
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