Verification of Parameterised FPGA Circuit Descriptions with Layout ...

BIBLIOGRAPHY 178
[30] IEEE. IEEE standard VHDL language reference manual, IEEE Std 1076-1987, March
1988.
[31] G. Jones and M. Sheeran. Circuit design in Ruby. In J. Staunstrup, editor, Formal
Methods for VLSI Design, pages 13–70. North-Holland/Elsevier, 1990.
[32] G. Jones and M. Sheeran. Relations and refinement in circuit design. In C. Morgan and
J. Woodcock, editors, 3rd Refinement Workshop, Springer Workshops in Computing.
Springer-Verlag, 1991.
[33] J. J. Joyce. Formal verification and implementation of a microprocessor. In G. Birtwistle
and P. A. Subrahmanyam, editors, VLSI Specification, Verification and Synthesis.
Kluwer, 1988.
[34] M. Kaufmann and J. S. Moore. An industrial strength theorem prover for a logic based
on Common Lisp. IEEE Transactions on Software Engineering, 23(4):203–213, April
1997.
[35] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing.
Science, 220(4598):671–680, 1983.
[36] A. Krukowski and I. Kale. Simulink/Matlab-to-VHDL route for full custom/FPGA rapid
prototyping of DSP algorithms. In Proc. DSP’99: Matlab DSP Conference, Tampere,
Finland, November 1999.
[37] C. Kulkarni, G. Brebner, and G. Schelle. Mapping a domain specific language to a
platform FPGA. In Proc. DAC’04: 41st Design Automation Conference, pages 924–
927, 2004.
[38] L. Lamport and L. C. Paulson. Should your specification language be typed? ACM
Trans. Program. Lang. Syst., 21(3):502–526, 1999.
[39] P.-Z. Lee and Z. M. Kedem. Mapping nested loop algorithms into multidimensional
systolic arrays. IEEE Trans. Parallel and Distributed Systems, 1(1):64–76, 1990.
[40] M. Lesser, W. M. Meleis, M. M. Vai, S. Chiricescu, W. Xu, and P. M. Zavracky. Rothko:
A three-dimensional FPGA. IEEE Design and Test of Computers, 15(1):16–23, 1998.