Verification of Parameterised FPGA Circuit Descriptions with Layout ...

BIBLIOGRAPHY 177
[19] H. Gelernter. Realization of a geometry-theorem proving machine. In J. Siekmann and
G. Wrightson, editors, Automation of Reasoning: Classical Papers on Computational
Logic 1957–1966, volume 1, pages 99–124. Springer-Verlag, 1983.
[20] H. Gelernter, J. R. Hansen, and D. W. Loveland. Empirical explorations of the geometry-
theorem proving machine. In J. Siekmann and G. Wrightson, editors, Automation of Rea-
soning: Classical Papers on Computational Logic 1957–1966, pages 140–150. Springer-
Verlag, 1983.
[21] M. Gordon, R. Milner, and C. Wadsworth. Edinburgh LCF: a mechanised logic of
computation, volume 78 of LNCS. Springer-Verlag, 1979.
[22] M. J. C. Gordon. HOL: A proof generating system for higher-order logic. In G. Birtwistle
and P. Subrahmanyam, editors, VLSI Specification, Verification and Synthesis, pages
73–128. Kluwer, 1988.
[23] J. Greene, E. Hamdy, and S. Beal. Antifuse field programmable gate arrays. Proceedings
of the IEEE, 81(7):1042–1056, 1993.
[24] S. Guo and W. Luk. Compiling Ruby into FPGAs. In W. Moore and W. Luk, editors,
Proc. FPL’95: Field Programmable Logic and Applications, volume 975 of LNCS, pages
188–197. Springer-Verlag, 1995.
[25] S. Guo and W. Luk. Producing design diagrams from declarative descriptions. In
S. Yand, J. Zhou, and C. Li, editors, Proc. 4th Intl. Conf. on CAD/CG, pages 1084–
1093. SPIE, 1995.
[26] S. Guo and W. Luk. An integrated system for developing regular array designs. J.
Systems Architecture, 47(3-4):315–337, 2001.
[27] R. Hindley. The principal type scheme of an object in combinatory logic. Trans. Amer.
Math. Soc., 146:29–60, 1969.
[28] J. Hughes. Why functional programming matters. Computer Journal, 32(2):98–107,
1989.
[29] M. Huth and M. Ryan. Logic in Computer Science. Cambridge University Press, 2004.