Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 7. CONCLUSION AND FUTURE WORK 174 chip in operation. We have showed that distributed specialisation makes the process of verifying the specialisation of designs easier than lower-level approaches [80] and we have suggested that it should be quicker, though we have not quantitatively evaluated the execution speed of a HDL-level distributed specialisation process. Distributed specialisation in Quartz is an area that is definitely worthy of further investi- gation. In particular the addition of particular constructs to to the language to support run-time reconfiguration directly, as have been demonstrated for Pebble [15], could be in- vestigated. This would support a higher-level interface to run-time reconfiguration than the current capabilities using virtual multiplexer blocks [47]. 7.4.5 Properties of N-Dimensional Combinators The new class of n-dimensional combinators we introduced in Section 6.6 show the potential to substantially simplify the description of certain kinds of circuits, particularly those that manipulate multiple multi-dimensional data sources. Initial investigations also indicate that they could be used to clearly describe the translation of some classes of imperative function descriptions based on nested loops into hardware. The definition of an n-dimensional combinator suggests that it should be possible to prove useful theorems such as retiming and serialisation for all n-dimensional combinators at once, even though the description of the fully general case is substantially more complicated that the combinator for any particular dimension. Theorems that are valid for this entire class of combinators could be extremely useful since, even if complicated to prove, they would only need to be proved once. It is also worth investigating the different ways of mapping n-dimensional descriptions into two-dimensional FPGA hardware and, if there are multiple good ways of doing this, under what situations each is optimal.
Bibliography [1] A. Aggoun and N. Beldiceanu. Extending CHIP in order to solve complex scheduling and placement problems. J. Mathematical and Computer Modelling, 17(7):57–73, 1993. [2] M. J. Alexander, J. P. Cohoon, J. L. Colflesh, J. Karro, and G. Robins. Three- dimensional field-programmable gate arrays. In Proc. IEEE Intl. ASIC Conf., 1995. [3] P. Alfke. Efficient Shift Registers, LFSR Counters and Long Pseudo-Random Sequence Generators, Xilinx Application Note 052, July 1996. [4] J. M. Arnold. S5: The architecture and development flow of a software configurable processor. In Proc FPT’05: IEEE Conf. Field Programmable Technology, to appear. [5] D. Basin, H. Kuruma, K. Takaragi, and B. Wolff. Verification of a signature architecture with HOL-Z. In Formal Methods 2005, volume 3582 of LNCS, pages 269–285. Springer- Verlag, 2005. [6] N. Beldiceanu and M. Carlsson. Sweep as a generic pruning technique applied to the non- overlapping rectangles constraint. In T. Walsh, editor, Proc. Constraint Programming 2001, volume 2239 of LNCS, pages 377–391. Springer-Verlag, 2001. [7] P. Bjesse, K. Claessen, M. Sheeran, and S. Singh. Lava: hardware design in Haskell. In ICFP ’98: Proc. 3rd ACM SIGPLAN Intl. Conf. on Functional programming, pages 174–184. ACM Press, 1998. [8] R. Boulton, A. Gordon, M. Gordon, J. Harrison, J. Herbert, and J. V. Tassel. Experience with embedding hardware description languages in HOL. In V. Stavridou, T. F. Melham, and R. T. Boute, editors, IFIP TC10/WG 10.2 Intl. Conf. on Theorem Provers in Cir- 175
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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