Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 7. CONCLUSION AND FUTURE WORK 174
chip in operation.
We have showed that distributed specialisation makes the process of verifying the specialisa-
tion of designs easier than lower-level approaches [80] and we have suggested that it should
be quicker, though we have not quantitatively evaluated the execution speed of a HDL-level
distributed specialisation process.
Distributed specialisation in Quartz is an area that is definitely worthy of further investi-
gation. In particular the addition of particular constructs to to the language to support
run-time reconfiguration directly, as have been demonstrated for Pebble [15], could be in-
vestigated. This would support a higher-level interface to run-time reconfiguration than the
current capabilities using virtual multiplexer blocks [47].
7.4.5 Properties of N-Dimensional Combinators
The new class of n-dimensional combinators we introduced in Section 6.6 show the potential
to substantially simplify the description of certain kinds of circuits, particularly those that
manipulate multiple multi-dimensional data sources. Initial investigations also indicate that
they could be used to clearly describe the translation of some classes of imperative function
descriptions based on nested loops into hardware.
The definition of an n-dimensional combinator suggests that it should be possible to prove
useful theorems such as retiming and serialisation for all n-dimensional combinators at once,
even though the description of the fully general case is substantially more complicated that
the combinator for any particular dimension. Theorems that are valid for this entire class of
combinators could be extremely useful since, even if complicated to prove, they would only
need to be proved once.
It is also worth investigating the different ways of mapping n-dimensional descriptions into
two-dimensional FPGA hardware and, if there are multiple good ways of doing this, under
what situations each is optimal.