Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 7. CONCLUSION AND FUTURE WORK 172 construct. Parallel compositions or series compositions could potentially be annotated with explicit co-ordinates, or left to follow their default layout interpretation, as appropriate. This reduces the link between functional and non-functional (layout) description which, while it is often desirable, can sometimes be limiting – for example, when placing binary trees the ideal functional description is not a particularly good layout. 7.4.2 Less User Interaction In Proofs One issue with our proof environment is the handling of recursive size functions using Is- abelle’s recdef construct. At present our approach is to manually convert the automatically generated definitions into primitive recursion and it would definitely be possible to automate this process, however it is only valid for a (large) subset of Quartz blocks. It should be possible to get general size functions working by proving appropriate congruence rules to direct the automatic recdef termination proofs however recdef is a closed box and it will probably be necessary to closely examine and possibly change the Isabelle/HOL source code to find and correct the problems. While we achieved extremely good levels of automation, there appears to be potential to make some considerable improvements. Firstly, we would advocate further investigation into how the layout theorems regarding series and parallel composition can be better utilised by the automatic proof tools. There appears to be no reason why these theorems should need to be applied manually and many blocks that use composition could be proved much more easily if compositions were decomposed by the theorem prover correctly. We would also suggest that more experimentation with the ideal configuration of rule sets for the classical reasoner and simplifier to maximise effectiveness. We have generated scripts which specify specific rule sets for each theorem proof in the Quartz compiler but a better mechanism would be to specify these rule sets as defaults and prove theorems using simply “auto”. This is not as easy as it sounds since we are presently generating different scripts for different types of theorems and some sort of compromise solution would need to be found that performed as well on all types of theorem as the current proof-specific method. Another avenue that might be worth investigating is to combine multiple logics and provers
CHAPTER 7. CONCLUSION AND FUTURE WORK 173 to achieve better automation. While Quartz combinators are usually high-order blocks and require a high-order formalism to verify their layouts, Quartz circuits tend to be parameterised purely by integer or boolean parameters. As such, it is possible that Quartz libraries could be verified in higher-order logic and these proofs could be in some way be treated as axiomatic in proofs for a whole circuit using a different prover with a different formalism. The ACL2 theorem prover [34] is known for supporting very high levels of automation but proves theorems in the first-order Boyer-Moore logic [9], it is possible that a combination of Isabelle and ACL2 could produce better results than Isabelle alone. A major practical difficulty that would need to be overcome here is ensuring the soundness of the interaction between the two different logics. 7.4.3 Integrating Layout and Functional Verification In this work we have developed a shallow embedding of Quartz designed specifically to enable the verification of design layouts. It seems slightly paradoxical to maintain two different verification systems, one for functionality and one for layout, when the two could potentially be combined into a single embedding within a theorem prover. To support full functional reasoning (some limited reasoning about functional properties is already possible) QuartzLayout would need to be extended with a timing model to allow the data values on wires to be properly modelled in synchronous circuits. It is likely that a deep embedding of Quartz, rather than a shallow semantic embedding, would be the best way to combine functional and layout verification in a single environment. We have already laid the foundations for the definition of such an embedding by defining a formal semantics of Quartz in HOL and this function could be translated into an Isabelle implementation to provide a meaning function for the deep embedding. 7.4.4 Run-time Reconfiguration In Chapter 5 we demonstrated the ability of our layout framework to support the specialisation of designs. Dynamic specialisation of designs at run-time is potentially a highly worthwhile activity, with performance gains outweighing the time required to reconfigure a
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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