Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 7. CONCLUSION AND FUTURE WORK 168 7.3 Comparison with Related Work To our knowledge, ours is the only work which addresses the issue of generating and verifying parameterised hardware libraries with explicit placement information and support for recur- sively and iterative described structures. However, other work has taken different approaches to the problem. 7.3.1 VHDL with Explicit Co-ordinates VHDL and Verilog can be used with absolute placement co-ordinates specified using “RLOC” constraints for Xilinx architectures. VHDL does not provide any particular support for placement in particular, however it can be extended with user-defined functions to implement the equivalent of our maxf and sum operations. VHDL does not support higher-order functions, however, so these would need to be coded explicitly for each hardware arrangement. Nevertheless, our theorem proving verification framework could be applied to VHDL designs. The potential for the use of a few dozen key theorems to automate proofs is severely reduced by the lack of higher-order functions however theorem proving can still be used to verify first-order placement co-ordinates. Size functions for each VHDL entity would probably need to be entered manually, although they could possibly be inferred in a similar way to Quartz providing a suitable subset of the language is used. VHDL allows the combination of behavioural and structural design styles within a single description and if this was done then verification of the correctness of entity size functions would probably be impossible without incorporating a theoretical model of how behavioural descriptions are elaborated into structural hardware. 7.3.2 Relative Placement in Pebble Pebble has been extended with support for relative placement [49]. The Pebble system uses new language constructs to provide below, beside, below for and beside for capabilities and a functional specification has been given for a procedure which compiles relative positions into absolute co-ordinates. The Pebble system is clean and effective at describing many
CHAPTER 7. CONCLUSION AND FUTURE WORK 169 common hardware constructs, however it contains several flaws which are not present in our approach. Firstly, by limiting itself to “conventional” arithmetic and logical expressions the Pebble system can not infer conditional branches in block sizes and is forced to select the maximum possible size of conditionals – something which can introduce inefficiency since circuits may not be placed as compactly as possible. Compaction of circuits with conditionals can be achieved using partial evaluation, however this requires that the final design is not parameterised in any variables which appear in conditional expressions. With the Pebble system layout correctness is achieved by design, through reliance on simple beside and below placement and the use of block size inference. However the Pebble system does not meet our own, more stringent, definition of correctness – for example, it may generate incorrect layouts when the size of each iteration of a loop is different. The insistence on using relative placement is also limiting and means that pathological cases such as the irregular grid example we described in Section 4.7 can not be described. On the other hand, the Pebble system does have some advantages over our framework. Firstly, it is much simpler and easier to implement in other languages, such as VHDL. By limiting itself to basic arithmetic and boolean expressions hardware may not be laid out completely optimally, however the expressions it does generate are simpler than those generated by the Quartz system which often contain conditionals or maxf/sum functions which have not been optimised away by the limited number of optimisations applied by the Quartz compiler. Finally, by incorporating beside and below as language constructs the Pebble system can express n-ary placement relationships more easily than can be done with Quartz. Quartz combinators are blocks like any other and have a fixed arity so can only be parameterised by a certain number of other blocks. Combinators can be parameterised by block vectors however this creates an unwanted type constraint that all blocks must have the same type. The Pebble system is designed to support placement of iteratively described circuit descriptions and does not detail how recursive blocks should be handled. This also causes problems for the compilation of Quartz layouts (see Section 3.7.4) however our general infrastructure does support recursive size functions.
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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