Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 7. CONCLUSION AND FUTURE WORK 166 have been unable to implement our system for generating parameterised placed VHDL from Pebble, although we are confident of its design and do not foresee any difficulties with this. There is currently no support for generating parameterised Pebble when Quartz blocks have recursive size expressions. There are a number of possible solutions to this problem that we have discussed, though we have not implemented them. The only totally general solution would be to allow Pebble expressions to contain recursive functions, which is not difficult although it is slightly untidy. We would recommend that recursive size expressions should be eliminated where possible by attempting to compute the transitive closure of the recursion. The verification framework also appears to work well for a wide variety of descriptions, rang- ing from library combinators to real circuits such as the median filter described in Section 6.3. However, we have learnt some important lessons about the relative ease of verifying different kinds of Quartz structures. Circuits described iteratively can generally be verified relatively easily using the extensive range of theorems in the QuartzLayout library developed for maxf and sum. The theorems in the Structures theory which can be applied to easily prove intersection theorems for loops are particularly useful since the proof goals tend to be quite complicated but are all of the same basic structure. Verification of recursively defined Quartz blocks is less automated. The compiler’s trans- lation into Isabelle recdef recursive definitions is correct but the definitions are not easily utilised by the theorem prover. We have had much more success with defining blocks using primitive recursion – however this is not a completely general approach. Proofs for recursive size functions require induction, however generally after this the automated proof tools are effective at completing the proof. Two important lessons have been learnt from the verification of our example circuits. Firstly, that the size inference process produces better results than expected and the need for manual specification of size functions is much less than was initially presumed. Secondly, that the relational nature of Quartz seriously complicates layout reasoning in some cases. The success of the size inference process is such that for most real circuits it is likely that size inference will be used almost all of the time, with manual size expressions only specified
CHAPTER 7. CONCLUSION AND FUTURE WORK 167 occasionally. Manual size expressions are still necessary, in order to describe the size of primitive blocks or blocks which should reserve more space on the FPGA than they actually require – for example, so that larger designs can be swapped into the same area using run- time reconfiguration. However, the present verification framework requires the verification of the validity and containment of size expressions generated from the inference algorithm and these proof goals could be mostly eliminated if proof of the correctness of the inference algorithm itself could be built into the Isabelle embedding 1 . That Quartz directional abstraction complicates layout reasoning is a slightly unexpected result since it is generally regarded as simplifying functional reasoning. The use of the definite description operator to define the values of internal signals using a block’s predicate as generated by the semantic function Bβ makes it difficult to use the actual values of these signals (unless they are defined very simply). It is possible that the mechanism for resolving Quartz directions could be coded in Isabelle and used to extract the real values however since the algorithm is incomplete it is difficult to see how the necessary properties could be established formally. Despite this, internal signals do not tend to cause problems most of the time because it is not actually necessary to resolve their value. Since Quartz is one of the few languages with directional abstraction this would also not be an issue if the verification framework were applied to another language. We have also shown how the layout infrastructure can be used as part of a system of distributed self-specialising Quartz blocks to transparently specialise hardware when one or more input values are known at compile-time. The limitations of our current framework for carrying out distributed specialisation are discussed in Section 5.3 however even with these limitations it can be a useful tool for carrying out some simple optimisations on generated hardware without requiring any significant designer effort. HDL-level specialisation is particularly important for placed hardware libraries because it allows designs to be compacted as logic is eliminated from circuits. This is not something that can be achieved with low level specialisation of the synthesised design because placement constraints are only parameterised in the high-level description. 1 It would not be possible to totally eliminate all containment proof obligations, since it still remains necessary to prove that no block exists to the left or below of (0, 0)
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Chapter 5 Specialisation In this ch
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CHAPTER 5. SPECIALISATION 111 // Ha
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CHAPTER 5. SPECIALISATION 113 circu
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