Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 7. CONCLUSION AND FUTURE WORK 166
have been unable to implement our system for generating parameterised placed VHDL from
Pebble, although we are confident of its design and do not foresee any difficulties with this.
There is currently no support for generating parameterised Pebble when Quartz blocks have
recursive size expressions. There are a number of possible solutions to this problem that we
have discussed, though we have not implemented them. The only totally general solution
would be to allow Pebble expressions to contain recursive functions, which is not difficult
although it is slightly untidy. We would recommend that recursive size expressions should be
eliminated where possible by attempting to compute the transitive closure of the recursion.
The verification framework also appears to work well for a wide variety of descriptions, rang-
ing from library combinators to real circuits such as the median filter described in Section 6.3.
However, we have learnt some important lessons about the relative ease of verifying different
kinds of Quartz structures.
Circuits described iteratively can generally be verified relatively easily using the extensive
range of theorems in the QuartzLayout library developed for maxf and sum. The theorems
in the Structures theory which can be applied to easily prove intersection theorems for loops
are particularly useful since the proof goals tend to be quite complicated but are all of the
same basic structure.
Verification of recursively defined Quartz blocks is less automated. The compiler’s trans-
lation into Isabelle recdef recursive definitions is correct but the definitions are not easily
utilised by the theorem prover. We have had much more success with defining blocks using
primitive recursion – however this is not a completely general approach. Proofs for recursive
size functions require induction, however generally after this the automated proof tools are
effective at completing the proof.
Two important lessons have been learnt from the verification of our example circuits. Firstly,
that the size inference process produces better results than expected and the need for manual
specification of size functions is much less than was initially presumed. Secondly, that the
relational nature of Quartz seriously complicates layout reasoning in some cases.
The success of the size inference process is such that for most real circuits it is likely that
size inference will be used almost all of the time, with manual size expressions only specified