Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 7. CONCLUSION AND FUTURE WORK 165
classical reasoner to verify the layouts of many blocks without requiring any user intervention
at all. We demonstrate how this verification infrastructure can be applied to a range of useful
combinators.
In Chapter 5 we illustrate the use of our system to specialise designs when certain input values
are known. We introduce the idea of distributed specialisation with self-specialising Quartz
blocks and show that removing central control of HDL-level specialisation has significant
advantages in terms of easing verification and faster processing for dynamic specialisation
applications. We show that HDL-level specialisation of placed designs is able to achieve
design compaction, unlike lower level approaches which operate on a fully routed circuit
or placed netlist. We demonstrate the specialisation of a parallel multiplier and show that
specialisation with compaction substantially increases performance and reduces the logic area
required to implement the function.
Chapters 6 demonstrates the use of our layout framework with several complete circuit de-
scriptions, including a median filter and matrix multiplier. We introduce a new n-dimensional
combinator for use in multi-dimensional circuit descriptions and show that the cubical version
of this combinator can describe a matrix multiplication operation more clearly than existing
combinators. We also demonstrate how Quartz combinators can be used at a low-level to
pipeline circuits using the in-slice flip-flops of the Xilinx Virtex-II FPGA architecture. We
show that for many circuits, manually placed designs are compiled quicker, require less logic
area, have a higher maximum clock frequency and a lower power consumption than when
automatically placed.
7.2 Evaluation
The layout generation system works well and we have succeeded in generating parameterised
Pebble libraries from a variety of Quartz descriptions. In most cases maxf and sum functions
are eliminated from the output in favour of conditional expressions by compiler optimisations
– and these conditionals could themselves be eliminated by replacing them with Pebble
conditional generation of the different alternatives if we so wished. The current version of
the Pebble compiler does not currently support generation of parameterised VHDL so we