Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Chapter 7
Conclusion and Future Work
In this final chapter we review the work reported in this thesis, its contribution and potential
for future development.
7.1 This Thesis’ Contribution
In this thesis we have described the design, implementation and applications of a framework
for describing and verifying parameterised FPGA circuits with layout information.
In Chapter 3 we describe how we can extend Quartz with additional constructs to describe
placed circuits. We show how two functions – maxf and sum – are sufficient to describe
the placement and size of iterative structures. We demonstrate how the size of blocks can
be inferred and also provide a mechanism for sizes to be specified manually. We show how
high-order Quartz descriptions with layout information can be compiled into parameterised
hardware libraries with high-order parameters removed.
Chapter 4 describes an infrastructure for the verification of Quartz circuit layouts using the
Isabelle theorem prover. We give a formal semantics for Quartz descriptions in HOL and
provide HOL interpretations of layout correctness. Using a modified Quartz compiler we are
able to automatically generate semantic definitions for Quartz blocks and proof obligations for
layout correctness. The compiler can also generate proof scripts using Isabelle’s simplifier and
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