Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 162
One invariant we have seen across all circuit examples is that manually placing designs
significantly reduces the time taken for the place and route stage of the compilation process
to execute, with the reduction ranging from 14% for the unpipelined matrix multiplier to
92% for the unpipelined adder tree. This result is not overly surprising, since the place and
route stage has been reduced to just routing, however it is beneficial to confirm it since it
could have been the case that the denser placements specified by the user constraints would
increase the routing time by more than is saved by avoiding automatic placement.
Another fairly firm conclusion is that in almost all cases 4 manually placed designs require
less logic area than automatically placed ones. The logic mapping specified by the manual
constraints is denser than that used by the automatic tools and reductions in area of 40% are
commonly achieved, with a maximum of 61% area reduction observed for the unpipelined
adder tree. In one case the manual mapping for a butterfly circuit used less than 70% of
the device resources while the automatic mapping and placement was unable to fit the same
circuit onto the device. Manual placement is clearly significantly superior here.
The effectiveness of manual placement on positively influencing maximum clock frequency
depends on other constraints. Given a homogenous environment, simulated annealing is able
to generate circuits with equivalent or better performance by discovering high speed routing
paths between cells that humans would not consider sensible - for example, the placed 24-bit
pipelined binomial filter circuit is 35% slower than the automatically placed version. However,
when other constraints are affecting the layout simulated annealing does not perform so well
and the regular layout constraints can produce significant performance gains.
The kind of constraints that affect simulated annealing appear to be use of the fast carry chain
circuitry, which forces some cells to be laid out vertically, and level of device utilisation which
reduces the ability to the placer to find high-speed routes through less densely packed logic.
For pipelined bitonic merger butterfly networks, the 4-bit manually placed circuit utilises
only 28% of the device runs 14% slower than the automatically placed version - however the
8-bit version utilises 55% of the device and runs 48% faster than the automatically placed
version.
Manual placement often produces better results than simulated annealing for unpipelined
4 The exception to this we observed was the binomial filter circuit, where we deliberately specified a less
dense logic mapping in order to achieve a better aligned layout.