Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
CHAPTER 6. LAYOUT CASE STUDIES 160 Proof By moving the delay out of the instantiation of cube cell and exploiting the timeless property of wiring blocks to re-organise 3 . We can use a particular instance of this theorem for the cube and manipulate it so the resulting circuit is implementable to give: Theorem 29 cubex,y,zR = [ ˜ z D, ˜ z D, id] ; cubex,y,z(R ; [D, id, id]) ; [id, z D, z D] This theorem can then be used to generate synchronisation registers for the interfaces of the matrix multiplier when we pipeline it. We undertake a layout verification of the cubical matrix multiplier using the previous cor- rectness proofs for col, grid, the multiplier and ripple adder. In the cube block we need to add further explicit type annotations to eliminate some type unknowns because the Is- abelle/HOL theory of zip is not sufficiently detailed to describe the full types. This indicates that a full theory of zip (and indeed tplapl and tplapr) is required, and not just the simple approximation contained in the theory Inbuilt, even though the inbuilt blocks do not affect layout. Otherwise proofs are mostly automatic, with some intervention required for series compositions and expanding the definition of word transpose. Appendix D.3 gives the full Quartz description and some proofs for the matrix multiplier circuit. 6.6.4 Results We generate a circuit that multiples two 2 ×2 matrices together to produce a 2 ×2 matrix as output and evaluate two of these components on the Virtex-II. Table 6.8 shows the results for this circuit. Power consumption was measured at a clock frequency of 16.625Mhz. As can be seen the placed version is out-performed by the automatically placed version for both the pipelined and unpipelined variants in terms of maximum clock frequency, although the percentage difference is small. The power consumption figures present a confusing picture, 3 Actually, proving that the D element can be moved out of cube cell is a difficult and fiddly proof, however cube cell is designed to allow this to take place so we will gloss over this at this point.
CHAPTER 6. LAYOUT CASE STUDIES 161 Slices Util. t-PAR (s) Max freq. (Mhz) Pwr (mW) Unpipelined/Auto 1568 31% 14 23.7 276 Unpipelined/Placed 1413 28% 12 23.0 108 Pipelined/Auto 1542 30% 16 30.7 192 Pipelined/Placed 1476 29% 12 28.9 204 Table 6.8: Results for matrix multiplier circuit with no clear trends emerging. The pipelined, placed version actually consumes more power than the the unpipelined version, which is unexpected since previous results have shown pipelining reduces power consumption for many kinds of circuits [85]. However, the overall power consumption of the circuit is so low it is possible that any real effects are being overwhelmed by noise. Because of the shape of the placed matrix multiplier it is not possible to fit more onto the Virtex device however by increasing the pipelining (by pipelining the multipliers themselves for example) the design could be run and evaluated at a higher clock frequency. The placed version does place & route faster than the unplaced circuit and consumes fewer resources on the chip, so could still be superior in some situations where the small difference in maximum clock frequency is not significant. It is possible that an alternative layout for the cube combinator would produce better results. With the z signals being used for the accumulator data path there are long wires between the respective elements of each grid. 6.7 Evaluation and Conclusions For the five example designs in this chapter we have seen a range of results for our four evaluation metrics: logic area, place and route time, maximum clock frequency and power consumption. At important realisation that manual placement is not an optimisation method per se but rather a way of exerting more control over the compilation process. The way in which that control is exercised determines whether the circuits generated are better or worse in some way than those that would have been generated automatically.
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CHAPTER 6. LAYOUT CASE STUDIES 161<br />
Slices Util. t-PAR (s) Max freq. (Mhz) Pwr (mW)<br />
Unpipelined/Auto 1568 31% 14 23.7 276<br />
Unpipelined/Placed 1413 28% 12 23.0 108<br />
Pipelined/Auto 1542 30% 16 30.7 192<br />
Pipelined/Placed 1476 29% 12 28.9 204<br />
Table 6.8: Results for matrix multiplier circuit<br />
<strong>with</strong> no clear trends emerging. The pipelined, placed version actually consumes more power<br />
than the the unpipelined version, which is unexpected since previous results have shown<br />
pipelining reduces power consumption for many kinds <strong>of</strong> circuits [85]. However, the overall<br />
power consumption <strong>of</strong> the circuit is so low it is possible that any real effects are being<br />
overwhelmed by noise. Because <strong>of</strong> the shape <strong>of</strong> the placed matrix multiplier it is not possible<br />
to fit more onto the Virtex device however by increasing the pipelining (by pipelining the<br />
multipliers themselves for example) the design could be run and evaluated at a higher clock<br />
frequency.<br />
The placed version does place & route faster than the unplaced circuit and consumes fewer<br />
resources on the chip, so could still be superior in some situations where the small difference<br />
in maximum clock frequency is not significant.<br />
It is possible that an alternative layout for the cube combinator would produce better results.<br />
With the z signals being used for the accumulator data path there are long wires between<br />
the respective elements <strong>of</strong> each grid.<br />
6.7 Evaluation and Conclusions<br />
For the five example designs in this chapter we have seen a range <strong>of</strong> results for our four<br />
evaluation metrics: logic area, place and route time, maximum clock frequency and power<br />
consumption.<br />
At important realisation that manual placement is not an optimisation method per se but<br />
rather a way <strong>of</strong> exerting more control over the compilation process. The way in which that<br />
control is exercised determines whether the circuits generated are better or worse in some<br />
way than those that would have been generated automatically.
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