Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 2. BACKGROUND AND RELATED WORK 7
FPGAs consist of a grid of programmable logic cells and programmable routing to connect
these computational elements together. The vast proportion of chip area is made up of
programmable routing resources. As well as basic programmable logic cells, many FPGA
architectures also include more complex hardware such as embedded RAMs, multipliers and
instruction processors.
The main component of each FPGA logic cell is typically an SRAM look-up table (LUT),
which can be programmed to implement any n-input logic function. Each logic cell usually
contains a flip-flop which can be connected to the output of the LUT and possibly other
specific logic designed to accelerate particular common functions.
FPGAs are programmed to adopt a particular configuration by loading a “bitstream”. This
is usually done at start-up but it is also possible reconfigure FPGAs at run-time, adapting
their function as they continue to process data. This bitstream is typically generated from a
high-level description in some kind of hardware description language.
2.1.1 Generating FPGA Circuits
The process of generating FPGA configurations from hardware descriptions is usually a
complex and time consuming process. Four major steps are:
1. Synthesis: generating a graph representing of logical expressions representing a design
from a higher-level hardware description. This could include the process of creating a
logical description from an imperative one, such as Handel-C [12].
2. Mapping: assigning logic graph nodes into devices resources such as look-up tables or
registers. Algorithms like FlowMap [13] can be used to achieve this.
3. Placement: the placement of mapped resources onto specific resources of the target
architecture. Automatic placement algorithms typically use heuristics such as simulated
annealing [35].
4. Routing: configuring the programmable routing fabric to connect the placed resources
together to implement the logic graph.