Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 159
block matmultcell (int n) (wire x in[n], wire y in[n], wire z in[n]) ∼
(wire z out[n], wire y out[n], wire x out[n]) {
x out = x in.
y out = y in.
((x in, y in), z in) ; fst (mult n) ; add n; z out at (0,0).
}
block matmult (int bits) (int x, int y, int z)
(wire mat1[y][z ][ bits ], wire mat2[z][x][ bits ]) ∼ (wire mat3[y][x][ bits ]) {
wire emptymat[y][x][bits].
wire mat trans[z][y][ bits ].
int i , j, k.
for i = 0..y−1 {
for j = 0..x−1 {
for k = 0..bits−1 { emptymat[i][j ][ k] = false. } . } . } .
mat1 ; word transpose bits (y, z) ; mat trans at (0,0).
(mat trans, mat2, emptymat) ;
cube (x, y, z, matmultcell bits) ;
converse (tplapl 2) ;
pi1 ;
mat3 at (0,0).
}
Figure 6.24: Quartz description of the 3D matrix multiplier
In the implementation of the functional cell we use the column ripple adder developed in
Section 6.2 and the placed parallel multiplier we described in Chapter 5.
We can pipeline this circuit by inserting registers on the z data path, since this is the
accumulator path. We can derive a general pipelining arrangement for nd using a retiming
theorem for a column:
Theorem 27 coln R = fst ( ˜
n D) ; coln (R ; D) ; [D −n , ˜
n D−1 ]
We can apply this to the n-dimensional combinator description to give a theorem for the
one-dimensional pipelining of an n-dimensional structure:
Theorem 28
ndn R = tplaprn−1 −1 ; fst (zip n−1 ; ˜
in D) ; tplaprn−1 ;
ndn (R ; tplapln−1 −1 ; fst D ; tplapln−1)
tplapln−1 −1 ; [D −in , zip n−1 ; ˜
in D−1 ; zip n−1 −1 ] ; tplapln−1