Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 157
nd2 (i1, i2) R = coli2 (rowi1 R)
ndn (i1, . . .,in) R = tplaprn−1 −1 ; fst (zip n−1 ) ; colin
swap ; snd tplapln−2 −1 ; rsh ; fst (zip 2,n−2 ) ;
tplapln−2 ; ndn−1 (i1, . . .,in−1) (ndcelln (x, R)) ;
tplaprn−2 −1 −1
; snd(zip2,n−2 ; swap) ; rsh ;
swap ; snd tplaprn−2 ;
snd(zip n−1 −1 ) ; tplapln−1
ndcelln (m, R) = tplapln−2 −1 ; fstswap ; lsh ; sndswap ; rsh ; fst tplapln−2 ;
been much discussed [38].
snd(aplm−1 −1 ) ; tplapl2 ; tplapr2 −1 ;
fst (tplaprn−1 ; R ; tplaprn−1 −1 ; swap) ;
lsh ; snd(swap ; aprm−1) ; fst tplaprn−2 −1 ;
lsh ; sndswap ; tplaprn−2
Figure 6.22: Description of an n-dimensional meta-combinator
Figure 6.22 illustrates our n-dimensional combinator description. This combinator is defined
recursively with a base case of n = 2 (grid ). For n = 3 the description of nd simplifies to
that of cube and ndcell simplifies to the description of cube cell.
The definition of an n-dimensional combinator description raises the tantalising possibility of
being able to prove theorems for all higher-dimensional combinators as a single theorem. For
example, we could prove a theorem that could totally pipeline an n-dimensional array taking
the pipelining theorem for a grid as the base case. Alternatively we could investigate how to
serialise [45] higher-dimensional descriptions into lower dimensional ones (e.g. converting a
4D description into 3D, 2D, 1D equivalents with appropriate multiplexers to manipulate the
input signals).
Unfortunately, the descriptions of nd and ndcell themselves are complex and fiddly, even
though most individual steps are just describing simple wiring re-arrangements. Since most
of the commands are simple wiring they are easy to reason about, for example tplapl and tplapr
are timeless and thus registers can be moved through them easily. The complex description
does seem to suggest that it could be a candidate for employing mechanised theorem proving.