Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 155
block cube (int x, int y, int z, block R (‘a, ‘b, ‘c) ∼ (‘c, ‘b, ‘a))
(‘a x d[z][y], ‘b y d[z][x], ‘c z d[y][x]) ∼
(‘c z r[y][x], ‘b y r[z][x], ‘a x r[z][y]) {
((x d, y d), z d) ;
fst (zip 2) ;
col (z, swap ; rsh ; fst (zip 2) ;
grid (x, y, cube cell (x, R)) ;
snd (converse (zip 2)) ; rsh ; fst swap ; lsh) ;
snd (converse (zip 2)) ;
(z r, (y r, x r)).
}
Figure 6.19: A Quartz description for cube as a column of grids
block cube cell (int n, block R (‘a, ‘b, ‘c) ∼ (‘c, ‘b, ‘a))
((‘c z[n], ‘a x), ‘b y) ∼ (‘b y2, (‘c z2[n], ‘a x2)) {
((x,y), z) ;
snd (converse (apl (n−1))) ; rsh ;
fst (tplapr 2 ; R ; converse (tplapl 2) ; swap) ;
lsh ; snd (swap ; apr (n−1)) ;
((y2, x2), z2).
}
Figure 6.20: The cube cell re-wiring block
This cube combinator creates a grid of not R blocks but cube cell blocks. This is a wiring
block with a description shown in Figure 6.20. It splits the full z vector that has been
“packaged” up with the x vector and extracts the signal that is for this element, connects it
to R and then appends the z output of R back into the z vector. The whole operation rotates
the z vector as the value is extracted from the left and appended to the right, meaning that
the next block will extract the correct (different) z signal and by the end of the row the
resulting z signals are all neatly packed into the vector. Figure 6.21 illustrates this structure.
6.6.2 Describing N-dimensional Combinators
The description in Figure 6.20 uses two new language constructs: tplapl and tplapr. These
are tuple append blocks that function in much the same way as apl and apr do for vectors,
adding or removing elements from the left or right of a tuple. These must be defined as
language constructs that are statically parameterised because otherwise they are not valid
within the Quartz type system which requires that tuples are fixed-arity data structures. We