Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 6. LAYOUT CASE STUDIES 154 y_in x_in x_in y_in x_in x_in R R R R R R R R z_out z_in R R R R x_out x_out y_out x_out x_out y_out Figure 6.18: A cubical circuit can be viewed as a column of grids. each other, however the wiring is somewhat complex as the z dimension connections need to be routed through the x and y connections between the two grids. We can do this by “folding” the extra dimensional signals into a tuple with one of the “standard” grid dimensions and extracting them as needed. This can be done using the zip n,m language construct which converts an n-tuple of vectors into an m-dimensional vector of tuples. A pre-requisite for this operation is that the vectors are the same size in the dimensions that are being zipped and it turns out that there is only one valid way of carrying this out. Figure 6.19 shows how a cube combinator can be written in terms of col and grid. Note the re-arrangement of the domain tuple into a pair of a tuple of (x d, y d) and z d while the same has been done to the range tuple. Pairs are actually extremely powerful mechanisms - they allow us to split signals into a part to perform operations on and a part to ignore. The conversion of the 3-tuple of domain/range signals into a pair allows the use of the fst and snd blocks to control the applications of the zip 2 block - we will show how this transformation can be included in the description shortly.
CHAPTER 6. LAYOUT CASE STUDIES 155 block cube (int x, int y, int z, block R (‘a, ‘b, ‘c) ∼ (‘c, ‘b, ‘a)) (‘a x d[z][y], ‘b y d[z][x], ‘c z d[y][x]) ∼ (‘c z r[y][x], ‘b y r[z][x], ‘a x r[z][y]) { ((x d, y d), z d) ; fst (zip 2) ; col (z, swap ; rsh ; fst (zip 2) ; grid (x, y, cube cell (x, R)) ; snd (converse (zip 2)) ; rsh ; fst swap ; lsh) ; snd (converse (zip 2)) ; (z r, (y r, x r)). } Figure 6.19: A Quartz description for cube as a column of grids block cube cell (int n, block R (‘a, ‘b, ‘c) ∼ (‘c, ‘b, ‘a)) ((‘c z[n], ‘a x), ‘b y) ∼ (‘b y2, (‘c z2[n], ‘a x2)) { ((x,y), z) ; snd (converse (apl (n−1))) ; rsh ; fst (tplapr 2 ; R ; converse (tplapl 2) ; swap) ; lsh ; snd (swap ; apr (n−1)) ; ((y2, x2), z2). } Figure 6.20: The cube cell re-wiring block This cube combinator creates a grid of not R blocks but cube cell blocks. This is a wiring block with a description shown in Figure 6.20. It splits the full z vector that has been “packaged” up with the x vector and extracts the signal that is for this element, connects it to R and then appends the z output of R back into the z vector. The whole operation rotates the z vector as the value is extracted from the left and appended to the right, meaning that the next block will extract the correct (different) z signal and by the end of the row the resulting z signals are all neatly packed into the vector. Figure 6.21 illustrates this structure. 6.6.2 Describing N-dimensional Combinators The description in Figure 6.20 uses two new language constructs: tplapl and tplapr. These are tuple append blocks that function in much the same way as apl and apr do for vectors, adding or removing elements from the left or right of a tuple. These must be defined as language constructs that are statically parameterised because otherwise they are not valid within the Quartz type system which requires that tuples are fixed-arity data structures. We
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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