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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 6. LAYOUT CASE STUDIES 153<br />

block cube (int x, int y, int z, block R (‘a, ‘b, ‘c) ∼ (‘c, ‘b, ‘a))<br />

(‘a x d[z][y], ‘b y d[z][x], ‘c z d[y][x]) ∼<br />

(‘c z r[y][x], ‘b y r[z][x], ‘a x r[z][y]) {<br />

‘a xs[x+1][z][y]. ‘b ys[y+1][z][x]. ‘c zs[z+1][y][x].<br />

int ix, iy, iz.<br />

}<br />

xs[0] = x d. ys[y] = y d. zs[z] = z d.<br />

x r = xs[x]. y r = ys[0]. z r = zs[0].<br />

for ix = 0..x−1 {<br />

for iy = 0..y−1 {<br />

for iz = 0..z−1 {<br />

(xs[ix ][ iz ][ iy ], ys[iy+1][iz ][ ix ], zs[ iz+1][iy ][ ix ]) ;<br />

R ;<br />

(zs[ iz ][ iy ][ ix ], ys[iy ][ iz ][ ix ], xs[ix+1][iz ][ iy]).<br />

} .<br />

} .<br />

} .<br />

Figure 6.17: cube combinator defined iteratively <strong>with</strong> explicit internal signals<br />

generalises easy to the n-dimensional case where extra dimensions can simply be added.<br />

We can describe a cube combinator iteratively as shown in Figure 6.17 in terms <strong>of</strong> explicit<br />

internal signals. Multiple copies <strong>of</strong> the R block are instantiated and connected to internal<br />

signals xs, ys and zs that hold values flowing along the x-axis, y-axis and z-axis respectively.<br />

This definition uses three different internal signals rather than declaring a single vector <strong>of</strong><br />

internal signals <strong>with</strong> an extra dimension, this is because the signals flowing along each axis<br />

can have different types - as illustrated in the type signature for the R block and the cube<br />

block itself.<br />

This interpretation <strong>of</strong> a cube also identifies the final important element <strong>of</strong> our convention –<br />

that the (0, 0, 0) point is located at the front, left <strong>of</strong> a cubical structure. This is reflected in<br />

the indexes chosen to connect to the R block in the loop. While this is a short description it<br />

is quite complex and has no particularly obvious layout interpretation.<br />

We can envisage a cube as a 1D array <strong>of</strong> 2D arrays. We exploit this to represent a cube as a<br />

column <strong>of</strong> grids. This kind <strong>of</strong> description immediately gives the cubical circuit a 2D layout<br />

interpretation – as grids laid out vertically on top <strong>of</strong> one another. Figure 6.18 illustrates the<br />

wiring involved in this kind <strong>of</strong> arrangement. In this example two grids are placed on top <strong>of</strong>

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