Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 151
6.6 Matrix Multiplier
Our final circuit example is a matrix multiplier circuit. Matrix multiplication is a simple
operation that has applications in many scientific computing applications as well as branches
of digital signal processing. The multiplication of two matrices requires a large number of
multiplication and addition operations and there is considerable potential for parallelisation,
making a hardware implementation attractive.
Band matrix multipliers have previously been described as systolic grid-shaped circuits using
Ruby [44, 68]. These descriptions were difficult to relate to a simple specification of matrix
multiplication as a set of multiply-accumulate operations. We will describe our system in a
clearer manner using a new combinator that describes 3D circuits.
We are motivated to create new higher-dimensional combinators by the realisation that a
combinator with a certain dimension is appropriate for processing data with a particular
dimension. For example, a one-dimensional array such as a row can process one dimensional
data, while a grid can process two dimensional data (or two one-dimensional data streams).
However, the confusion with mapping an operation such as matrix multiplication onto a grid
arises from the fact that the input data is two two-dimensional data sources and the output is
two dimensional, while the grid itself only has 4 1-dimensional interface points in its domain
and range. If we can describe higher dimensional combinators, such as cubical structures,
then potentially we can describe circuits that operate on this kind of data much more clearly.
An important point to note is that we are talking about multi-dimensional circuit descrip-
tions, which are not the same as multi-dimensional circuits. Three dimensional FPGAs
have been proposed [2, 17, 40, 51], however four dimensional and higher-dimensional FP-
GAs pose interesting implementation difficulties. An alternative is to attempt to realise
higher-dimensional FPGA circuitry on standard two dimensional silicon. Schmit proposes
drawing on three and four dimensional topologies to increase the wiring density on stan-
dard two-dimensional silicon [72]. What we propose is designing combinators which describe
multi-dimensional circuits but which we expect to realise on two-dimensional silicon.
Any higher-dimensional array can be flattened onto a 2D grid in a number of ways. We
propose higher-dimensional combinators that have an implicit layout interpretation on the