Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 150
plies for the unpipelined circuits and is not surprising because we have deliberately specified
a less-dense packing for this circuit, using the lift block to align registers with the adders and
thus using only one out of each two slice flip-flops in these columns. In the unpipelined cir-
cuits we are also not utilising the in-slice flip-flops of the adder columns which could be used
to implement the coefficient delay. If we had specified a denser packing for the unpipelined
circuit then we would use b × n fewer slices (where b is the number of bits and n the number
of stages) – saving over 1000 slices for the 32-bit, 32 stage circuit.
The manually placed designs have better maximum clock frequencies than the automatically
placed ones when there is no pipelining and significantly worse performance when pipelined.
For example, the placed 32-bit filter runs 14% faster than the unplaced version when un-
pipelined, but 30% slower when pipelined.
The clock frequency result is important, since it indicates that simulated annealing has
achieved better results for the pipelined circuit regardless of the circuit size. The difference
between the placed and unplaced circuits does nonetheless differ depending on the circuit
size, with the placed circuit 35% slower for 24-bit data but 30% slower for the larger 32-bit
data variant.
This result is consistent with previous research [77] which indicated that placed adder circuits
not employing the carry chain were outperformed by circuits placed using simulated anneal-
ing. It shows that without the vertical placement constraint enforced by use of the carry
chain simulated annealing can place cells where it likes and find high speed paths between
cells which humans would probably not have considered. In the absence of other constraints,
simulated annealing can therefore find irregular layouts which are better than what a human
would consider reasonable.
Interestingly although for the pipelined circuits the manually placed variants have lower
maximum clock frequencies, when run at the same clock frequency they consume between
1.5% and 13.1% less power. This indicates that manual placement has a role to play even
in circuits such as this one where it leads to a decreased maximum potential performance by
specifying a denser logic mapping and reducing circuit power consumption. If a 24-bit filter
that can run at 50Mhz is desired then the placed circuit is clearly superior – it will compile
quicker, use less logic area and consume significantly less power while running at that speed.