Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 149
block lift (int n, block R ‘a ∼ ‘b) (‘a i) ∼ (‘b o) {
i ; R ; o at (0, n).
}
Figure 6.15: The lift combinator can be used to place blocks at a certain y-offset
Slices Util. t-PAR (s) Max freq. (Mhz) Pwr (mW)
24-bit data
Unpipelined/Auto 3074 60% 29 15.2 -
Unpipelined/Placed 3111 61% 11 17.2 -
Pipelined/Auto 3817 75% 37 153.2 648
Pipelined/Placed 3114 61% 16 99.7 588
26-bit data
Unpipelined/Auto 3336 65% 31 15.0 -
Unpipelined/Placed 3370 66% 12 17.4 -
Pipelined/Auto 4140 81% 38 146.0 684
Pipelined/Placed 3373 66% 19 103.8 612
28-bit data
Unpipelined/Auto 3597 70% 34 13.9 -
Unpipelined/Placed 3629 71% 13 16.8 -
Pipelined/Auto 4463 87% 46 120.3 732
Pipelined/Placed 3632 71% 17 73.5 636
32-bit data
Unpipelined/Auto 4128 81% 38 13.4 -
Unpipelined/Placed 4150 81% 14 15.4 -
Pipelined/Auto 5108 100% 61 137.1 768
Pipelined/Placed 4149 81% 14 96.0 756
Table 6.7: Results for a 2 binomial filter circuits
1 × 2 we use the lift combinator, shown in Figure 6.15. lift instantiates a block at a certain
y-offset, leaving empty space underneath it.
6.5.2 Results
We compile a 32-stage binomial filter for several different bitwidths and implement two on the
Virtex-II device. We evaluate versions without any pipelining and with bit-level pipelining,
with no input/output synchronisation.
The results for the variants of this circuit, shown in Figure 6.7, are particularly interesting.
Firstly, this is the first circuit where the manual placement has not always led to a denser
logic mapping than the automatic algorithms, with several manually placed versions actually
requiring marginally more slices than their automatically placed equivalents. This only ap-