Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 147
Slices Util. t-PAR (s) Max freq. (Mhz) Pwr (mW)
4-bit data
Unpipelined/Auto 2559 50% 16 25.1 -
Unpipelined/Placed 1439 28% 6 27.2 -
Pipelined/Auto 2559 50% 19 76.1 252
Pipelined/Placed 1439 28% 11 65.5 360
6-bit data
Unpipelined/Auto 3874 76% 37 18.6 -
Unpipelined/Placed 2114 41% 12 19.7 -
Pipelined/Auto 3887 76% 36 70.4 432
Pipelined/Placed 2127 42% 14 67.6 396
8-bit data
Unpipelined/Auto 5118 100% 69 10.0 -
Unpipelined/Placed 2778 54% 19 17.6 -
Pipelined/Auto 5118 100% 74 36.4 648
Pipelined/Placed 2812 55% 22 53.8 516
10-bit data
Unpipelined/Auto - >100% - - -
Unpipelined/Placed 3453 67% 19 15.8 -
Pipelined/Auto - > 100% - - -
Pipelined/Placed 3496 68% 18 57.4 624
the relationship:
Table 6.6: Results for 2 64-input bitonic merger circuits
Theorem 26 R : α ∼ wire ⇒ R ; D = register R
6.4.3 Results
We generate a bitonic merger circuit that merges two lists of 32 8-bit numbers pipelined and
unpipelined for four different bit widths. Two of these circuits are placed on the Virtex-II
chip.
Figure 6.6 shows the results for these circuits. The placed version takes up significantly
fewer logic resources on the device than the unplaced version. In fact, for the 10-bit data the
unplaced circuit the synthesis tools report that the design can not actually be mapped onto
the device, while the placed version uses less than 70% of the available resources.
The picture for our other metrics is less clear, although manual placement clearly produces
significant improvements in maximum clock frequency for unpipelined designs the same is
not always the case for the pipelined versions. The same mixed picture is observed with