Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 6. LAYOUT CASE STUDIES 144 block riffle (int n) (‘a x[2∗n]) ∼ (‘a y[2∗n]) attributes { height = 0. width = 0. }{ int i. for i = 0..n∗2−1 { if (i mod 2 == 0) {y[i] = x[i/2]. } else { y[i ] = x[n+i/2]. } . } . } Figure 6.10: Iterative riffle operation block spacer (int w, int h) (‘a i) ∼ (‘a o) attributes { width = w. height = h. }→ i = o. block spacer (int w, int h) (‘a i1, ‘b i2) ∼ (‘b o1, ‘a o2) attributes { width = w. height = h. }→ (o1, o2) = (i2, i1). Figure 6.11: Two sided and four sided spacer blocks explicit vector indexes however it can also be defined using append blocks: vecpair = apl2 −1 ; snd [−] −1 = apr2 −1 ; fst [−] −1 The proof of this relationship is easy. The butterfly combinator can be instantiated with any R block to produce a variety of different butterfly networks. Its structure has a clear layout interpretation imparted by the combinator blocks it utilises: map will arrange the R blocks of each stage of the butterfly vertically and each stage will be laid out horizontally next to the previous stage by the rcomp block. This is a very dense arrangement and it is possible that for some architectures there may be insufficient routing resources available to route the complex wiring network between each stage of the butterfly. To avoid this problem the butterfly combinator can have a spacer block added to the description of each stage. A spacer is a block which is functionally identical to the identity block but is defined to have a non-zero size, it can thus be used to produce empty space in designs. Figure 6.11 illustrates two spacer blocks for use in two-sided and four-sided circuit arrange- ments. They are declared as instances of an overloaded spacer identifier which are selected between depending on their type. For the butterfly combinator the spacer component can
CHAPTER 6. LAYOUT CASE STUDIES 145 gr_lut gr_lut gr_lut gr_lut gr_lut gr_lut eq_lut eq_lut eq_lut eq_lut eq_lut eq_lut mux mux mux mux mux mux mux mux mux mux mux mux Figure 6.12: 6-bit 2-sorter circuit be placed anywhere within the rcomp parameter composition since the type is polymorphic, however the logical place to put the spacer in order to put room between each butterfly stage is next to the map instantiation - it can then be given the desired width and any height (less than the expected height of the map instantiation) and the series composition layout will ensure that this space is left free. 6.4.2 Implementing a bitonic merger The butterfly circuit we evaluate is a network of 2-sorters. This is a bitonic merger circuit which merges together two sorted lists. The merger is bitonic because the order of the input lists must be opposed – i.e. if one is ascending then the other must be descending or vice versa. We design a 2-sorter circuit which operates on n-bit data values and lay it out as a 4 × n block as shown in Figure 6.12. The first two columns are a comparator which outputs a control signal to the multiplexers to select the maximum and minimum values. The butterfly sorting network can be pipelined by inserting registers between each stage, replacing the R block by R ; D We can state the correctness of a pipelining arrangement with the following theorem: Theorem 24 R ; D = D ; R ⇒ butterfly n R = butterfly n (R ; D) ; D −n Proof This requires a lemma about repeated series composition:
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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Appendix C Placed Combinator Librar
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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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