Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 144
block riffle (int n) (‘a x[2∗n]) ∼ (‘a y[2∗n])
attributes { height = 0. width = 0. }{
int i.
for i = 0..n∗2−1 {
if (i mod 2 == 0) {y[i] = x[i/2]. } else { y[i ] = x[n+i/2]. } .
} .
}
Figure 6.10: Iterative riffle operation
block spacer (int w, int h) (‘a i) ∼ (‘a o)
attributes { width = w. height = h. }→ i = o.
block spacer (int w, int h) (‘a i1, ‘b i2) ∼ (‘b o1, ‘a o2)
attributes { width = w. height = h. }→ (o1, o2) = (i2, i1).
Figure 6.11: Two sided and four sided spacer blocks
explicit vector indexes however it can also be defined using append blocks:
vecpair = apl2 −1 ; snd [−] −1 = apr2 −1 ; fst [−] −1
The proof of this relationship is easy.
The butterfly combinator can be instantiated with any R block to produce a variety of
different butterfly networks. Its structure has a clear layout interpretation imparted by the
combinator blocks it utilises: map will arrange the R blocks of each stage of the butterfly
vertically and each stage will be laid out horizontally next to the previous stage by the rcomp
block.
This is a very dense arrangement and it is possible that for some architectures there may
be insufficient routing resources available to route the complex wiring network between each
stage of the butterfly. To avoid this problem the butterfly combinator can have a spacer block
added to the description of each stage. A spacer is a block which is functionally identical
to the identity block but is defined to have a non-zero size, it can thus be used to produce
empty space in designs.
Figure 6.11 illustrates two spacer blocks for use in two-sided and four-sided circuit arrange-
ments. They are declared as instances of an overloaded spacer identifier which are selected
between depending on their type. For the butterfly combinator the spacer component can