Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 143
Figure 6.8: A butterfly network of degree 4 (2 4 = 16 inputs)
block butterfly (int n, block R (‘a, ‘a) ∼ (‘a, ‘a)) (‘a l [m]) ∼ (‘a r[m]) {
const m = 2 ∗∗ n.
l ; rcomp (n,
riffle (m/2) ;
pair (m/2) ;
map (m/2, vecpair ; R ; converse (vecpair)) ;
converse (pair (m/2))
) ; r.
}
6.4.1 Butterfly Combinator
Figure 6.9: Quartz butterfly combinator
A butterfly network is an arrangement of functional blocks as shown in Figure 6.8. The
network is characterised by repeated instantiations of the same, or similar functional blocks,
with a particular wiring arrangement between them. There are a number of different ways
of describing butterfly networks in Quartz and one of the simplest is shown in Figure 6.9.
This combinator uses repeated composition to connect together multiple instantiations of
the the functional block R with a wiring arrangement described by riffle and pair. The pair
block converts a one dimensional vector into a two dimensional vector of pairs. The riffle
operation splits a vector into two halves and then combines them in an interleaved fashion,
an iterative version of this wiring block is given in Figure 6.10.
The vecpair block converts a two element vector into a pair (tuple) of elements and its
converse performs the opposite operation. The Quartz vecpair block is defined referencing