Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 142
Slices Util. t-PAR (s) Max freq. (Mhz)
Default synthesis tool configuration
Automatic 2401 47% 116 2.95
Placed 1317 26% 73 5.38
200ns timing constraint
Automatic 2401 47% 127 4.36
Placed 1317 26% 62 5.35
150ns timing constraint
Automatic 2401 47% 158 4.82
Placed 1317 26% 91 6.04
Table 6.5: Results for a median filter with 32-bit data values and a window size of 11
on the maximum clock frequency, though less so for the manually placed design. The time
taken by the place & route process increases substantially as the timing constraint is made
more stringent, although the manually placed version is processed quicker for all constraint
settings.
The performance of the automatically and manually placed versions are similar. However,
both circuits use only a tiny proportion of the available logic resources and we have previously
observed that automatic place & route seems to have more of an advantage at low utilisations.
Table 6.5 gives the results for a larger median filter design, with 32-bit data values and a
window size of 11. This design uses significantly more of the chip and the placed design has
the clear advantage over the automatically placed version, in terms of both place & route
time and maximum clock frequency. The clock frequency advantage is greatest when no
timing constraint is specified, where the placed version is 82% faster, however even when the
difference is minimised for the 200ns timing constraint the placed version is still 22% faster
- and takes half the time to process.
We do not record the power consumption of the median filter circuit because it runs at too
slow a clock frequency to make this worthwhile. We could pipeline the design if there was a
desire to increase its operating frequency.
6.4 Butterfly Network
Butterfly circuits are characterised by their intensive wiring patterns. Such networks are
commonly used in applications such as computing a Fast Fourier Transform.