Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 141
shift registers
insert
locater
compactor
Figure 6.7: Median filter realised on a Virtex-II
Slices Util. t-PAR (s) Max freq. (Mhz)
Default synthesis tool configuration
Automatic 247 4% 26 32.2
Placed 147 2% 19 37.7
30ns timing constraint
Automatic 247 4% 27 37.2
Placed 147 2% 19 37.1
20ns timing constraint
Automatic 247 4% 71 42.5
Placed 147 2% 54 41.1
Table 6.4: Results for a median filter with 8-bit data values and a window size of 5
Figure 6.7 shows the logic resources used when a median filter is realised on a Virtex-II chip.
The relative layout of the different components of the circuit can be clearly seen.
6.3.3 Results
We synthesise two different sizes of the median filter for a Virtex-II chip. Results for the
smaller version, with 8-bit data values and a window size of 5, are shown in Table 6.4.
We compared the results for three different configurations of the Xilinx synthesis tools. The
place & route tool can be configured with a desired timing constraint on the resulting circuit,
which the tool will attempt to meet. It can be seen that this does have a significant effect