Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 1. INTRODUCTION 5
pler, allowing the correctness of all specialised circuits to be established by proving
their equivalence to the original general circuit. We show that our layout framework
supports distributed specialisation and can be used to achieve design compaction dur-
ing specialisation of parameterised circuits, in contrast to more conventional low-level
approaches which eliminate unnecessary logic but do not compact the circuit. Speciali-
sation with compaction reduces the area on-chip that must be allocated to a circuit and
we demonstrate that it improves performance for a simple parallel multiplier design.
(Chapter 5)
5. We describe and verify the layout for five example circuits, including a median filter,
butterfly network and a matrix multiplier described using a new class of n-dimensional
combinators, and investigate the benefits of using user-specified placement constraints
during synthesis. We show that manually placed designs can be placed a d routed faster
and often have higher performance and lower power consumption while requiring less
logic area on a Xilinx Virtex-II device. Improvements of up to 80% in maximum clock
frequency and a 61% reduction in area are observed. (Chapter 6)
1.3 Organisation
The remainder of this thesis is organised as follows: Chapter 2 presents relevant background
information and related work. Chapter 3 introduces the layout description framework and
illustrates how circuit descriptions with layout information can be compiled. Chapter 4 de-
tails the layout verification environment and gives details of some key proofs. Chapter 5
introduces distributed specialisation and demonstrates the use of the layout framework to
produce specialised circuits. Chapter 6 describes the construction, verification and perfor-
mance of some example circuits. Chapter 7 evaluates this work, draws conclusions and
presents recommendations for future research.
Appendix A gives the full grammar of the extended Quartz language. Appendix B gives
the definitions and proofs in the verification environment for Quartz circuit layouts and
Appendix C gives example proofs for a variety of library combinators. Appendix D contains
some of the proofs for the layout correctness of the circuit examples in Chapter 6.