Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 139
s
a a2
f
eq
or2
d
f2
(a) lct cell (b) del cell in
through mode
(c) del cell in
compact mode
Figure 6.6: Cells making up various filter blocks
output an array of boolean values (d) which control the operation of the compactor block.
The value a is the value the locater is “looking for”, s is one of the elements in the state, f
is a boolean indicating whether the value has been located yet. Each lct cell compares its
state value with the a value and outputs d and f2 values which control the compactor.
The compactor is made up of a row of cells which use multiplexers controlled by the d output
of the corresponding lct cell. This mode signal configures the dell cell block into one of two
configurations: through mode (Figure 6.6(b)) and compact mode (Figure 6.6(c)).
The locater configures all compactor cells to the right of the first detected match to the
correct value (the same value could be within the current state multiple times) into through
mode. This has the effect of routing the detected value to the right, while the other values are
routed straight through. The value that appears on the rightmost output of the compactor
is discarded. The compactor outputs the correct n elements of the next state.
The midelem block is a simple wiring block which outputs the median value by extracting
the middle value from the sorted list.
6.3.2 Layout
We arrange the insert, locater and compactor blocks vertically roughly as shown in Figure 6.5.
lct cell is formed from an equality checker, composed of a column of and3 gates on top of
an or2 gate. del cell is implemented by two multiplexers arranged in adjacent columns.
The insert insertion-sort block is built from a row of min2 and max2 sorters, with each
bit implemented as a comparator function unit and another function unit operating as a