Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 138
new value
delays
insert
previous state
locater
compactor
next state
midelem
median value
Figure 6.5: Block diagram for the median filter
simply insert a value into the correct position in an already sorted list.
6.3.1 Circuit Design
Our design is loosely based on a state-machine based design previously described in Ruby [26],
however our realisation differs substantially and, we would suggest, is made much simpler by
using the full features of Quartz rather than basic Ruby relations 2 . Figure 6.5 shows the basic
architecture of our filter, with several blocks that operate on a current state and produce a
next state. This is essentially the state transition and output logic of a state machine and
this circuit can be composed with appropriate registers using the loop combinator.
The two inputs to this filter core are the previous state (a set of sorted values) and a single
new value. This new value is inserted into the sorted list by the insert block which implements
one stage of an insertion sort. If the state contains n elements then the output of the insert
block contains n + 1 elements, one of which (the oldest) must now be removed.
As well as being connected to the insert block the new value is also fed into an n-element
shift register, which is used to determine the value to remove to make the new state. The
locater carries this out, matching the value from n cycles ago with the values in the state
until the first match is found.
The locater is composed of a row of lct cells, which are shown in Figure 6.6(a). These cells
2 The Ruby design was however refined into a bit-level version, while we will concentrate on the word-level
circuit.