Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 137
Slices Util. t-PAR (s) Max freq. (Mhz) Pwr (mW)
Unpipelined/Auto 4872 95% 225 53.3 -
Unpipelined/Placed 1907 37% 19 65.5 -
Pipelined/Auto 4872 95% 142 123.0 1404
Pipelined/Placed 1908 37% 40 150.9 852
Table 6.2: Results for 7 adder trees
method. This appears to be a result of the Xilinx algorithm only packing, as a first preference,
“related” logic into the same slice. Thus, while the manually specified layout tends to use
both function generators in a slice, the automatic one prefers to use only one. This may
allow the Xilinx router to perform better and could explain why the automatically placed
single pipelined adder tree example requires more FPGA resources than the placed version
but still runs faster.
We measure the power consumption of the pipelined variants. Running at the same clock
frequency, the placed design consumes substantially less power (39% less dynamic power,
once the quiescent consumption of the development board is subtracted) than the unplaced
design, though it is unclear whether this is the result of the design using fewer logic resources
or of better routing.
6.3 Median Filter
Median filters are a special case of ranked order filtering. The median filtering operation is
widely used in digital image processing to remove noise and in a variety of other applications.
Our circuit will be restricted to one dimensional filtering, although the extension to a two
dimensional filter is not difficult.
A 1-dimensional median filtering operation involves “sliding” a filter window along a range
of values and selecting the median value from the elements currently within the window.
This can be achieved by sorting the elements and selecting the middle value - obviously the
window size must always be an odd number so that there is a middle element to select. In
our circuit the elements within the current window are stored and each cycle a new value
is inserted while the oldest is discarded. Since only one element differs between different
window positions we do not need to implement a full sorter but can simplify the circuitry to