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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 6. LAYOUT CASE STUDIES 136<br />

Slices Util. t-PAR (s) Max freq. (Mhz)<br />

Unpipelined/Auto 777 15% 48 61.5<br />

Unpipelined/Placed 406 7% 19 69.7<br />

Pipelined/Auto 777 15% 28 206.0<br />

Pipelined/Placed 406 7% 26 152.0<br />

Table 6.1: Results for a single adder tree<br />

R using the timeless pre-condition and split into two repeated anti-delays <strong>with</strong>in the parallel<br />

composition using the property that D is polymorphic:<br />

half 2 n ; [btreen(R ; D) ; D −n , btreen(R ; D) ; D −n ] ; R<br />

The induction hypothesis can then be used to complete the pro<strong>of</strong>.<br />

Using this combinator we generate a 6-level tree <strong>of</strong> 8-bit ripple adders, producing a circuit<br />

which adds together 64 input values. The manual placement is compared <strong>with</strong> the identical<br />

circuit compiled <strong>with</strong>out placement and using the Xilinx placement algorithm.<br />

6.2.3 Results<br />

Table 6.1 shows the results for placed and unplaced pipelined and unpipelined adder trees.<br />

“Util” is the percentage <strong>of</strong> resources utilised on the device, “t-PAR” is the amount <strong>of</strong> time<br />

required to place and route the circuit. As expected, pipelining increases the maximum clock<br />

frequency significantly (although far from the predicted theoretical maximum <strong>of</strong> ×8). It is<br />

also interesting to note that the manually placed design has worse performance than the<br />

automatically placed version when the circuit is pipelined, even though the manually placed<br />

version has been mapped into fewer Virtex slices.<br />

We also experimented <strong>with</strong> placing multiple adder trees on the <strong>FPGA</strong>. Table 6.2 illustrates<br />

the results for an <strong>FPGA</strong> loaded <strong>with</strong> 7 <strong>of</strong> the adder trees. The difference in the resources used<br />

by the placed and unplaced descriptions is very significant, and possibly partially responsible<br />

for the fact that the placed version now exhibits significantly higher performance than the<br />

unplaced version regardless <strong>of</strong> pipelining.<br />

The difference in the number <strong>of</strong> slices used is quite interesting. It implies that the process<br />

<strong>of</strong> packing primitives into slices automatically does so much less densely than the manual

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