Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 133
b
a
cout
Figure 6.1: Circuit diagram of the full adder block
block fadd ((wire a, wire b), wire cout) ∼ (wire cin, wire ans)
attributes { height = 1. width = 1. }{
wire xored ab.
(a,b) ; xor2 ; xored ab at (0,0).
(cin, xored ab) ;xorcy ; ans at (0,0).
(a, cin) ; muxcy xored ab ;cout at (0,0).
}
Figure 6.2: A full adder within a single Virtex 2 slice
All three primitive components within the fadd block are placed at co-ordinates (0, 0) indi-
cating that they should be located within the same slice. The xor2 block is a wrapper for the
Xilinx lut2 primitive which initialises the look-up table with the values necessary to produce
an xor function.
We have illustrated the full adder from the unpipelined ripple adder circuit, however, it is
possible to connect a pipeline register on the output ans signal in a series composition with
the xorcy block, all within the same slice. A full n-bit ripple adder can be formed using the
column combinator: (a, b) ; zip 2 ; π1 −1 ; coln fadd ; (cin, ans).
The verification of the fadd layout is a particular issue. Since the smallest meaningful element
in our layout framework is a block of size 1 ×1 (half a slice, for Virtex-II) and our framework
assumes a homogeneous grid of resources, it is not possible to verify the layout within the full
adder block. Instead, we reason about circuits using the full adder at the level of individual
full adders, assuming that fadd itself is correct. The xor2, xorcy and muxcy blocks (and fd
flip-flop primitives, if desired) are given a size of 0 × 0 to indicate that many can be packed
within a slice.
cin
ans